General Electric Company

Albert Andreas Maria Esser

Raymond Albert Fillion

Charles S Korman

Barry Scott Whitmore

A power semiconductor device package includes at least one power semiconductor device mounted onto at least one electrically and thermally conductive spacer having an upper end surface bonded to a back surface of the device; a substrate of hardened substrate molding material surrounding the semiconductor device and the spacer except for an active major surface of the device and an lower end surface of the spacer, a dielectric film overlying the device active major surface and a top side of the substrate, the dielectric layer having a plurality of holes aligned with predetermined ones of the contact pads; a top side patterned metal layer on the dielectric film including portions extending into the holes electrically and thermally connected to contact pads of the device; and a backside metal layer on a substrate bottom side electrically and thermally connected to the spacer lower end surface. Optional through-post structures can be employed to bring all electrical connections either to the top side of the device package or the bottom side. Optional heat sinks can be mounted to the top side, the bottom side, or both sides.

Growing community of inventors

Delafield, WI, United States of America

Albert Andreas Maria Esser