Agilent Technologies, Inc.

Albert An-Bon Yeh

Regina Nora Pabilonia

Robert William Kressin

Wei Liu

Arthur Fong

Paul Thomas Carson

Ling Liu

Thomas James Weaver

In one embodiment, a photo-imageable material is deposited on a circuit structure. The photo-imageable material is then exposed to a pattern of radiation, thereby polymerizing portions of the photo-imageable. Un-polymerized portions of the photo-imageable material are then removed to define a solder mask having solder deposition areas. Solder is then deposited in the solder deposition areas. A circuit structure that may be produced in accordance with this method is also disclosed.

Method and circuit structure employing a photo-imaged solder mask

A method for producing and tuning a packaged integrated circuit a) incorporates into a packaged integrated circuit design, at least one tunable circuit feature; b) fabricates a packaged integrated circuit in accordance with said packaged integrated circuit design; c) identifies a trimming point on the tunable circuit feature of said packaged integrated circuit, using an x-ray inspection system; d) relates coordinates of the trimming point to coordinates of a visible reference marker; e) utilizes the relationship between the visible reference marker and the trimming point to position a cutting tool over the trimming point; and f) utilizes the cutting tool to make one or more cuts into the packaged integrated circuit, until the tunable circuit feature has been acceptably modified at the trimming point.

Methods for designing and tuning one or more packaged integrated circuits

In a parallel design process for ICs, plural circuit features to be evaluated are laid out while designing an IC. Plural ICs are then fabricated and packaged. For a first packaged IC, an interior circuit feature coupled to at least one of the plural circuit features to be evaluated is identified. A trimming point on the interior circuit feature is identified using an x-ray inspection system; coordinates of the trimming point are related to coordinates of a visible reference marker; and the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. The cutting tool is used to cut into the first packaged IC until the interior circuit feature has been acceptably modified at the trimming point. Operation of the first packaged IC is compared to operation of a second packaged IC. Other parallel design processes are also disclosed.

Parallel design processes for integrated circuits

A circuit feature that is interior to a packaged integrated circuit is modified by first identifying a trimming point on the interior circuit feature using an x-ray inspection system. Coordinates of the trimming point are then related to the coordinates of a visible reference marker. The relationship between the visible reference marker and the trimming point is then used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the packaged integrated circuit, until the interior circuit feature has been acceptably modified at the trimming point.

Modification of circuit features that are interior to a packaged integrated circuit

Disclosed herein are methods for modifying an inner-layer circuit feature of a printed circuit board. A trimming point on the inner-layer circuit feature is identified using an x-ray inspection system. The coordinates of the trimming point are then related to the coordinates of a visible reference marker on the printed circuit board. Next, the relationship between the visible reference marker and the trimming point is used to position a cutting tool over the trimming point. Finally, the cutting tool is used to make one or more cuts into the printed circuit board, until the inner-layer circuit feature is acceptably modified at the trimming point.

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Colorado Springs, CO, United States of America

Albert An-Bon Yeh