International Business Machines Corporation

Albert Alfonse Slane

Gary Scott Delp

Philip Lynn Leichty

Jonathan W Byrn

Kevin Gerard Plotz

Mark William Branstad

Lee Anton Sendelbach

Todd Edwin Leonard

Brad L Brech

Jeffrey James Lynch

Gary Paul McClannahan

John Emery Nordman

Kenneth Dale Aaker

John Handley Shaffer

Fadi-Christian E Safi

Michael E Aho

Roch A Guerin

Arthur J Meyer, Iii

Rajendran Rajan

Robert John Manulik

Vinod Gerard Peris

David Richard Poulter

Phillip L Leichty

A method and apparatus are provided for implementing communications in a communications network. The apparatus for implementing communications includes a system interface to the communications network. A scheduler schedules enqueued cells and enqueued frames to be transmitted. A segmenter segments frames and cells in into cells or frames applied to a media adaptation block for transmission in a selected one of multiple modes.

Communications adapter for implementing communications in a network and providing multiple modes of communications

The present invention is a method and apparatus for reducing processing overhead using a stream data reassembly mechanism and at least one data buffer. The present invention pre-processes incoming frames before delivering the frames to system memory. When a first packet of an data stream is received, the data from the packet is placed into a data buffer. Information about the first packet is stored in a logical channel descriptor (LCD) to indicate that data exists in the current data buffer. As each subsequent packet in the data stream is received, the reassembly mechanism removes extraneous transmission data from the packet and checks the CRC of each trailer to qualify the data within the packet. After the data is qualified, the reassembly mechanism stores the data portion of the packet in the data buffer. This preprocessing of each packet continues until a predetermined condition is met. Once a predetermined condition is met, the reassembly mechanism will make the contents of the buffer available to the system. The reassembly may optionally associate a direct memory access (DMA) descriptor with the buffer and burst the contents of the buffer into system memory. The reassembly mechanism of the present invention thereby reduces the amount of data reception interrupts processed by the system and can also reduce the number of direct memory access data transfer across the system bus.

Apparatus and method for reassembling frame data into stream data

A method and apparatus are provided for user programmable packet to connection translation. When a data block is received, a protocol type for the received data block is identified based upon the media connection or port number for the recevied data block. A connection identification is formed utilizing a header of the received data block, responsive to the identified protocol type for the received data block. An instruction array is used with an arithmetic logic unit (ALU). Different code sequences are loaded into the instruction array based upon the user configured protocol type for a media connection of the received data block.

Method and apparatus for user programmable packet to connection translation

A method and Gigabit Ethernet communications adapter are provided for implementing communications in a communications network. A transmission queue is defined of data to be transmitted. A transmission rate is set for the transmission queue. Data to be transmitted are enqueued on the transmission queue. The transmission queue can be subdivided into multiple priority queues, for example, using time wheels, and a transmission rate is set for each transmission queue.

Communications methods and gigabit ethernet communications adapter providing quality of service and receiver connection speed differentiation

A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of instruction is evaluated. Responsive to the one-of instruction control, a next instruction pointer is generated. A one-of-and-jump instruction is evaluated. Responsive to the one-of-and-jump instruction control, a first next instruction pointer and a second next instruction pointer are generated. The second next instruction pointer is a destination instruction pointer for the one-of-and-jump instruction.

Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications

Provided is a system, method, and program for managing read and write requests to a cache to process enqueue and dequeue operations for a queue. Upon receiving a data access request to a data block in a memory, a determination is made as to whether any data block is maintained in a cache line entry in the cache. If so, a cache line entry maintaining the data block is accessed to perform the data access request. A first flag, such as a read flag, associated with the accessed cache line entry is set &ldquo;on&rdquo; if the data access request is a read request. Further, if the data access request is a write request to update the data block in the memory, a second flag, such as a write flag, associated with the cache line entry including the data to update may be set &ldquo;on&rdquo;. The update data may be data to be enqueued onto a queue, where the queue may be, but is not limited to, a circular buffer in the memory having a head and tail pointer. Still further, a cache line having each first flag set &ldquo;on&rdquo; and each second flag set &ldquo;on&rdquo; may be selected if there is no cache line having each first flag set &ldquo;on&rdquo; and each second flag set &ldquo;off&rdquo;, and entries in the selected cache line having their second flag set &ldquo;on&rdquo; may be flushed.

Method, system, and program for managing requests to a cache using flags to queue and dequeue data in a buffer

A method and apparatus are provided for implementing cyclic redundancy check (CRC) calculation for data communications in a communications system. CRC calculation apparatus includes a CRC tree structure receiving a first CRC input, a data input of N&minus;1 data input bytes; and a length input. The CRC tree structure includes a series of CRC trees. Each of the CRC trees has a seed CRC input, a fixed size data input and provides a CRC result output. The series of CRC trees are arranged in cascade with increasing data size inputs. A multiplexer control logic responsive to the length input selectively couples predefined data input bytes to predefined ones of the series of the CRC trees. The multiplexer control logic responsive to the length input couples the first CRC input to a selected one of the CRC trees; couples predefined CRC result outputs to predefined ones of the CRC trees; and utilizes a selected CRC tree to provide the overall CRC result.

Method and apparatus for implementing cyclic redundancy check calculation for data communications

A method and apparatus are provided for checksum verification with receive packet processing for communications over a data communications network. First a data communications connection is identified. Responsive to an identified data communications connection, a start of data packet is identified. Then a header checksum is calculated. A protocol checksum including a protocol pseudo header and data is calculated. An embedded processor structure is used for tracking packet state and running CRC calculations across received packets, and performing full checksum verification.

Method and apparatus for checksum verification with receive packet processing

A method and apparatus are provided for detecting and controlling data stream splicing in a stream of multimedia digital data over a distribution communications network. Sequential transport stream packets are obtained. Predetermined fields of each transport stream packet are interrogated to identify a splice in the data stream. A predetermined task is initiated responsive to an identified splice. In accordance with feature of the invention, one predetermined task initiated responsive to the identified splice includes masking the interrogated predetermined fields to mask the splice in the data stream.

Method and apparatus for detecting and controlling data stream splicing

A communication cell scheduler and scheduling method are provided to efficiently provide periodic activities and predetermined events. A timer descriptor is enqueued to a cell scheduler timing wheel. A timer expiration for the timer descriptor is identified and an address for a DMA descriptor is fetched from the timer descriptor. Then the DMA descriptor is enqueued to a DMA engine to execute the DMA descriptor.

Communications cell scheduler and scheduling method for providing

A method and apparatus are provided for resource allocation with guarantees. A resource allocator is coupled to a controller. The resource allocator allocates resources between a plurality of arrival processes. A dedicated resource pool and a shared resource pool are provided. When an arrival process is identified, the resource allocator obtains a predefined characterizing value for the identified arrival process. Responsive to the obtained predefined characterizing value, resource from one of the dedicated resource pool or the shared resource pool is allocated to the arrival process. The controller is utilized for tracking resource use and for providing the predefined characterizing value for each of the plurality of arrival processes. The dedicated resource pool has a predetermined capacity greater than or equal to the total of all the low threshold values for each of the arrival processes. The dedicated resource pool provides the guarantees with the shared pool providing statistical multiplexed resource use. The controller increments a usage charge for the arrival process when a resource is allocated and decrements the usage charge at the end of use of the allocated resource. The controller evaluates use for the identified arrival process and updates the predefined characterizing value.

Method and apparatus for resource allocation with guarantees

A method and apparatus are provided for enhanced scatter mode allowing user data to be page aligned in a memory. An adapter is coupled between a data communications network and the memory. A data packet including protocol header bytes is received from a data communications network by the adapter. A variable amount of data is specified for a first scatter page that contains the protocol header bytes. Subsequent sequential pages from the received data packet are transferred, for example, by direct memory access (DMA) operations, to real page addresses in the memory with the sequential pages transferred being page aligned in the memory. A page address is written to a DMA list stored in an adapter memory for the sequential pages transferred. A count value is incremented in a packet header of a number of pages transferred for each sequential page transferred. Responsive to transferring a last page from the received data packet, the first scatter page containing the packet header, the DMA list and the protocol header bytes is transferred to a separate address space in the memory. A small packet or single page size is specified for the adapter. When the total data size of a received packet is less than this small packet size, then the packet is not scattered. A single page mode is performed to transfer the small packet to the memory.

Method and apparatus for enhanced scatter mode allowing user data to be

A method and apparatus are provided for processing data transmissions across data communications networks including ATM networks, for example, to support arbitrary user action on transmit completes. Sequential transport stream packets are obtained. A predetermined field of each transport stream packet is interrogated to identify a DMA on transmit complete. The transmission of a last cell in each transport stream packet is identified. Then responsive to identifying the DMA on transmit complete, an address for a DMA descriptor is fetched from the transport stream packet. The DMA descriptor is enqueued to a DMA engine to execute the DMA descriptor.

Method and apparatus for direct memory access on transmit complete

A method and apparatus are provided for reducing processor interrupt processing time in a data processing system. The data processing system includes a system processor, a system memory and an adapter coupled to the system processor and the system memory. The adapter checks for an interrupt condition. Responsive to identifying an interrupt condition, the adapter transfers predetermined interrupt status information to the system memory. Then the adapter raises an interrupt to the system processor. The adapter uses a direct memory access (DMA) descriptor or a source address and a destination address to move the predetermined interrupt status information to the system memory.

Method for reducing processor interrupt processing time by transferring

An improved method and apparatus are provided for producing transmission control protocol (TCP) checksums using internet protocol (IP) fragmentation. A transmission control protocol module receives packet data to be transmitted and prepares a first internet protocol data fragment without a checksum for the received packet data. The first internet protocol data fragment is transmitted. Collecting checksum is performed during the transmission of the first internet protocol data fragment. Then an internet protocol header fragment including the collected checksum is transmitted.

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Oronoco, MN, United States of America

Albert Alfonse Slane