Altera Corporation

Alasdair Scott

Gregor Nixon

Steven Perry

Richard Louis Price

Jonathan C Park

Andrew Hall

Philippe Marti

Chris Dettmar

Larry Kong

Lingli Wang

Ziad M Abu-Lebdeh

A user logic design for a mask-programmable logic device ('MPLD') may be designed on a comparable or compatible user-programmable logic device ('UPLD') and migrated to the MPLD, or may be designed directly on an MPLD. If the design is designed on a UPLD, the constraints of the target MPLD&#x2014;i.e., differences between the devices&#x2014;are taken into account so that the migration will be successful. If the design is designed directly on an MPLD, constraints of a comparable compatible UPLD are taken into account if the user indicates that the design will be migrated to the UPLD for testing. This means that when a logic design is intended to be migrated back-and-forth between a UPLD and an MPLD, only the intersection of features can be used. To facilitate migration, fixed mappings between pairs of devices may be created.

Method for programming a mask-programmable logic device and device so programmed

A method for designing a system on a programmable logic device (PLD) includes translating a timing requirement of the system into a geographical constraint. Resources on the PLD are fitted onto locations on the PLD in response to the geographical constraint.

Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices to satisfy timing requirements

Programming software for mask-programmable logic devices provides a timing estimation to the user for the user's logic design during the compilation stage, notwithstanding that the software is not aware of the ultimate placement and routing of the design, which will be performed by the mask-programmable logic device supplier. The software includes a timing model based on actual delay measurements for different user designs in similar devices.

Timing analysis for programmable logic

A method for designing a system on a PLD is disclosed according to a first embodiment of the present invention. A logic design is optimized. Logic circuits from the logic design are mapped to resources on the PLD. At least some of the resources are fitted onto locations on the PLD by utilizing a user-specified procedure.

Method and apparatus for extending the capabilities of tools used for designing systems on programmable logic devices by registering a user specified procedure

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High Wycombe, United Kingdom

Alasdair Scott