Lucent Technologies Inc.

Agere Systems Inc.

Alaric Tate

Rose Fasano Kopf

Robert Alan Hamm

Robert William Ryan

Jinwook Burm

Christopher James Pinzone

Yu-Chi Wang

A method of fabricating a III-V heterostructure semiconductor device. The method includes the steps of forming at least one conductive post overlying a semiconductor region to form a structure, encapsulating the structure and the conductive post to form a planarized cured passivation layer, and exposing the conductive post through the planarized cured passivation layer to form the semiconductor device.

Method of fabricating a heterojunction bipolar transistor

The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO,layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.

Alignment techniques for epitaxial growth processes

The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd--Pt--Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

Method for making InP heterostructure devices

The specification describes a photolithography process using multiple exposures to form z-dimension patterns. Multiple exposures at different thickness levels are made using photomasks aligned with a latent image of alignment marks formed during the first exposure. The latent image is visible to the alignment system of commercial steppers.

Method of manufacturing schottky gate transistor utilizing alignment

Alignment techniques for photolithography utilizing multiple photoresist

The specification describes a technique for repairing wafer fractures that occur during wafer fabrication. The fractured pieces are joined edge-to-edge at the fracture line and bonded with epoxy adhesive. The method succeeds because the dimensions of the fracture line after bonding is within the reregistration tolerance of commercial step-and-repeat cameras and the reregistration capability of the camera allows normal exposure of sites that do not intersect the fracture line.

Repairing fractured wafers in semiconductor manufacturing

The specification describes a metal contact material optimized for diffused contacts to the buried emitter-base junction in DHBT devices. The metal contact material is a multilayer structure of Pd-Pt-Au which gives the required critical diffusion properties for low resistance contacts to the buried base layer without shorting to the collector layer.

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Chatham, NJ, United States of America

Alaric Tate