Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Alan Y Kwentus

Steven T Jaffe

Stephen Edward Krafft

David Hartman

Mark Dale

Alan Gin

Dorothy D Lin

Joyce Wang

Anders Hebsgaard

Jen-chieh Chien

Rocco J Brescia, Jr

Kelly Brian Cameron

Rocco Brescia

Hiroshi Suzuki

Kevin M Eddy

Jen-chieh (Jack) Chien

Henry Samueli

Tommy Yu

Charles Brooks

Kishore Kota

Thomas D Kwon

William Calvin Woodruff

Ali Abaye

Hassaan Aslam

Cho-Hsin J Wang

Abhijit Kumar Choudhury

Chung Ming Tu

Tarek Kaylani

Kadir Dinc

Chao Kun Lin

German Stefan Otto Feyh

Arash Farhoodfar

Jeffrey Tzeng

Steve Krafft

Jind-Yeh Lee

Richard Dale Tidstrom

Hebsgaard Anders

David Hwang

This disclosure presents a technique to include a packet sequence number and an integrity check value (ICV) into a data frame while maintaining a total number of transmitted bytes. A transmitting device includes circuitry that generates the ICV, inserts a transmitter packet sequence number into the data frame that includes a data packet including a payload, the data packet following a preamble and an interpacket gap (IPG) following the data packet. The circuitry also inserts the ICV into the data frame, and transmits the data frame, wherein inserting the ICV into the data frame reduces a size of the IPG while maintaining a total number of bytes in the data frame. A receiving device includes circuitry that receives the data frame, compares a receiver packet sequence number to the transmitter packet sequence number, and determines whether the transmitter packet sequence number is valid based on the receiver packet sequence number.

Light-weight mechanism for checking message integrity in data packets

A transceiver, a communication system and an associated method thereof for reducing overall power consumption and complexity of the transceiver that operates over short reach twisted pair cables. The analog front end (AFE) of the transceiver communicates over at least one twisted pair that is configured only for transmission of data streams and communicates over at least one twisted pair that is only for reception of data streams. The transceiver includes circuitry that generates multiplexed and demultiplexed data streams for communication with the analog front end. Additionally, the transceiver utilizes at least certain portions of signal processing circuitry and AFE of a 10 GBASE-T transceiver or the like.

Low power twisted pair coding scheme

An apparatus for operating a low data-rate (LDR) link and legacy switch at a high data-rate (HDR) includes a first block and a second block. The first block receives input signals from the legacy switch and generates identical output signals. The second block receives the identical output signals and generates an HDR signal for communication over the LDR link coupled to an access point. Further, a media access control (MAC) interface communicates data at a first data rate with an Ethernet PHY block including a first-in-first-out (FIFO) module and a buffer. The FIFO receives data from the MAC interface at the first data rate and transmits data at a second data rate. The buffer receives data from the Ethernet port at the second data rate and transmits the received data at the first data rate in response to detection of an end of packet.

Attachment unit interfaces for non-identical data rate links

Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1G PHY, while the output-side Ethernet module may include one or both of a 2.5G PHY and a 4G PHY.

Ethernet media converter supporting high-speed wireless access points

Transceiver architecture includes circuitry and a method to transmit and receive high speed WAP data over lower speed cabling such as Cat5e. The method begins by measuring quality of a wired bi-directional communications channel. The method continues by selecting a maximum possible data transmission rate over the wired bi-directional communications channel for the measured quality level and when the maximum possible data transmission rate is a reduced data transmission rate less than a maximum data transmission rate of the transceivers, proportionally adjusting clock rates of circuit elements of the first and second transceiver to transfer the data at the reduced data transmission rate. The method includes dividing data frames of the data to be transmitted N times, where N=number of layers of at least a portion of identical transceiver processing circuitry which is connected to twisted wiring pairs of the wired bi-directional communications channel.

2.5 GBPS/5GBPS ethernet communications over a full duplex communication channel

FEC (Forward Error Correction) decoder with dynamic parameters. A novel means by which FEC parameters may be encoded into, and subsequently extracted from, a signal stream to allow for adaptive changing of any 1 or more operational parameters that govern communications across a communication channel. FEC parameters are encoded directly into a data frame such that the data frame is treated identical to all other data frames within the signal stream. When the data frame actually includes FEC parameters, it is characterized as a CP (Control Packet) type. For example, when decoding an MPEG stream, an MPEG block that includes FEC parameters, that MPEG block is characterized as a CP MPEG block. The means by which FEC parameters are encoded and extracted from the signal stream allows for much easier adaptive modification of the manner by which signal are encoded, modulated, and processed within a communication system.

FEC (forward error correction) decoder with dynamic parameters

Ethernet media converter supporting high-speed wireless access

In a satellite gateway, data is transmitted over a downstream channel at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. The downstream data is parsed to extract data packets. The data packets are then loaded into packet queues based on an identifier within such packets. The queues represent a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers that may also be based on the current signal quality at a subscriber location. The parsed data traffic is processed based on the profile of the plurality of profiles to produce processed data traffic, and transmitted from the packet queues over a downstream channel.

Downstream time domain based adaptive modulation for DOCSIS based applications

In a DOCSIS based satellite gateway data is transmitted over a single downstream channel, at different throughput rates. Data destined for each subscriber/receiver is assigned a throughput rate depending upon the downstream signal quality of that subscriber/receiver. To accomplish this, the downstream DOCSIS MAC data is parsed to extract DOCSIS packets. The DOCSIS packets are then loaded into packet queues based on an identifier within such packets such as the MAC destination address or SID. Each of the queues represents a bandwidth efficiency or throughput rate that can be currently tolerated by specific subscribers based on the current signal quality being experienced at the subscriber location. A PHY-MAP describing the downstream data structure to be transmitted and inserted into the downstream data. Data is extracted from the packet queues in queue blocks as defined by the PHY-MAP. The queue blocks are modulated with transmission parameters appropriate for each queue block and transmitted to the DOCSIS based satellite modems. The satellite modems extract the PHY-MAP from the downstream data and use the information contained in it to demodulate and decode the queue for which they have sufficient downstream signal quality. Satellite modems measure and transmit downstream signal quality to the satellite gateway to be used to assigned traffic to the appropriate queues.

A modified ranging request in a broadband communications system. The modified ranging request includes a header, a management message header attached to the header, a management message payload attached to the management message header, and a CRC attached to the management message payload. The management message header enables bandwidth requests to be made by subscriber equipment without contention. The management message header also includes state of health information on the status of a downstream transmission for enabling a central location to determine how to assign subscribers to queues in an adaptive modulation scheme.

Modified range requests enabling bandwidth requests and state of health reporting

Herein described are at least a method and a system for implementing a high speed Tomlinson-Harashima Precoder. The method comprises using an L-tap transpose configuration of a Tomlinson-Harashima Precoder and processing a first discrete time sampled sequence using said L coefficients and L state variables by clocking the L-tap Tomlinson-Harashima Precoder using a clock signal wherein the clock signal has a clock rate equal to one half the symbol rate of the discrete time sampled sequence. In a representative embodiment, an L-tap Tomlinson-Harashima Precoder comprises a single integrated circuit chip, wherein the integrated circuit chip comprises at least one circuitry for processing a discrete time sampled sequence using L coefficients and L state variables by way of clocking the discrete time sampled sequence using a clock signal having a clock rate that is one half the symbol rate of the discrete time sampled sequence.

Method and system of providing a high speed Tomlinson-Harashima Precoder

Communications signal transcoder. A solution is provided to transcode a signal from a first signal type to a second signal type to ensure proper interfacing between devices that may operate using different signal types. For example, within a communication system, a first signal type (having a first modulation type, e.g., 8 PSK) may be received. The transcoder then ensures that this signal, after it has undergone any initial processing (such as tuning, down-converting, decoding, and so on), is encoded into a second signal type (having a second modulation type, e.g., QPSK) such that it can interface properly with a device for which the received signal is intended. This transcoder functionality may be implemented within discrete components, or it may alternatively be integrated within a functional block of an integrated circuit. This functionality may be implemented in a variety of communication systems including satellite, cable television, Internet, and others.

Communications signal transcoder

Methods and systems for modifying DOCSIS-based transmission paths for communication in higher frequency and/or wireless environments, such as wireless terrestrial communication systems and satellite communication systems. An inner turbo-code is combined with a DOCSIS based Reed-Solomon ('RS') forward error correction ('FEC') coding scheme, to produce a concatenated turbo-RS code (other FEC codes can be utilized). In phase and quadrature phase (&#x201c;I-Q&#x201d;) processing is utilized to enable relatively low cost up-converter implementations. The I-Q processing is preferably performed at baseband, essentially pre-compensating for analog variations in the transmit path. Power amplifier on/off control capable of controlling on/off RF power control of remote transmitters is modulated on a transmit cable to reduce the need for a separate cable.

Turbo-coding DOCSIS information for satellite communications

An integrated burst FSK receiver is provided to receive and interpret an RF signal using FSK modulation. The integrated burst FSK receiver uses a programmable RF local oscillator to mix a received signal down to an IF range or baseband, where it is filtered and sampled for subsequent digital processing. Digital filtering and detection are employed to improve overall bit error rate performance and receiver sensitivity. A programmable digital low-pass or band-pass filter can also be used to suppress interference. A matched filter correlator can be used for detection and symbol timing adjustment in one mode, while an adaptive frequency comparator can be used in another mode. Circuits are provided that estimate carrier offset, frequency deviation and signal strength. These measurements can then be used to optimize the receiver performance. A method for receiving and interpreting an RF signal using FSK modulation is also provided.

Integrated burst FSK receiver

Growing community of inventors

San Juan Capistrano, CA, United States of America

Alan Y Kwentus