Sandisk Technologies Inc.

Sandisk Corporation

Lexar Media, Inc.

Micron Technology Incorporated

Memory Corporation Plc

Sandisk Corproation

Memquest, Inc.

San Disk Corportion

Alan Welsh Sinclair

Barry Wright

Sergey Anatolievich Gorobets

Nicholas Thomas

Alan David Bennett

Peter John Smith

Kevin M Conley

Paul A Lassa

Liam Michael Parker

Robert David Selinger

Alan Douglas Bryce

Robert Edwin Payne

Richard Michael Taylor

Philip D Royall

Alan David Bennet

Natalia Victorovna Ouspenskaia

Ring bus architectures for use in a memory module are disclosed. A memory module may include a primary ring bus; a ring bus controller positioned on the primary ring bus; a secondary ring bus in communication with the primary ring bus via a first bus bridge; and a tertiary ring bus in communication with the secondary ring bus via a second bus bridge. The ring bus controller is configured to direct the first bus bridge to route data between the primary ring bus and the secondary ring bus and is configured to direct the second bus bridge to route data between the secondary ring bus and the tertiary ring bus.

Ring bus architecture for use in a memory module

Systems and methods for managing regular maintenance operations in combination with infrequent extended maintenance operations in a non-volatile memory are disclosed. The method may include executing portions of the extended maintenance over the course of multiple regular maintenance operations. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a previously programmed source block for an extended maintenance operation, sequentially selecting a plurality of previously programmed blocks for regular maintenance operations and dividing execution of the extended maintenance operation up such that the extended maintenance operation is completed in parts across the plurality of regular maintenance operations.

System and method for managing extended maintenance scheduling in a non-volatile memory

System and method for transferring data between a host system and a data storage system is provided. The system includes an interface that uses a file based protocol to transfer data between the data storage system and the host system, wherein the data storage system includes a first mass storage device and a second mass storage device; wherein the first mass storage device is a solid state non-volatile memory device and the second mass storage device is a non-solid state memory device. The first mass storage device is a flash memory device that operates as a primary storage device that stores data on a file by file basis. The second mass storage device is a magnetic disk drive that operates as secondary storage device and stores data received via a logical interface.

Systems and methods for a mass data storage system having a file-based interface to a host and a non-file-based interface to secondary storage

Systems and methods for balancing maintenance and programming host data across multiple maintenance source blocks in a non-volatile memory are disclosed. A memory system may include non-volatile memory and a controller configured to execute one or more of the steps of selecting a fixed plurality of maintenance source blocks for executing a balance cycle of maintenance and host writes across the selected fixed plurality of maintenance source blocks. The method interleaves moving of valid data from source blocks with host data writes to achieve a balance of free space generation and consumption for the balance cycle, while periodically reevaluating an overall interleave ratio and/or substituting other previously programmed blocks for one of the previously selected plurality during the balance cycle.

System and method for rescheduling host and maintenance operations in a non-volatile memory

A method is disclosed for only permitting data from a host to be written to a first non-volatile memory layer and only permitting data to be written into a second non-volatile memory layer via a maintenance operation over a single data path between the layers. The single data path may be an on-chip copy data path. A memory system includes a multi-layer non-volatile memory and data management circuitry, where the data management circuitry includes data flow path circuitry defining only a single data path for programming any data into the second layer. Maintenance manager circuitry and programming interleave circuitry in the data management circuitry are configured to select a maintenance schedule, and to interleave programming of host data with maintenance operation writes for the selected maintenance schedule only along the one or more data paths defined by the data flow path circuitry.

Method and system for programming a multi-layer non-volatile memory having a single fold data path

Non-volatile memory systems utilizing storage address tables are disclosed. A non-volatile memory system may include a non-volatile memory, a memory die command manager in communication with the memory, and a command manager in communication with the memory die command manager. The memory die command manager is configured to identify a free die of the memory to store data, where the free die of the memory is identified independent of a host logical block address associated with the data; store the data at a physical block address at the free die; and generate an entry in a first address table, the first address table associating the physical block address with a virtual logical block address. The command manager is configured to generate an entry in a second address table, the second address table associating the virtual logical block address with a host logical block address received with the host write command.

Non-volatile memory systems utilizing storage address tables

Ring bus architectures for use in a memory module are disclosed. A memory module may include a ring bus controller and a bus bridge positioned on a primary ring bus. The memory module also includes a secondary ring bus in communication with the bus bridge and a plurality of non-volatile memory units. The ring bus controller is configured to send a configuration command to the bus bridge via the primary bus ring, where the configuration command includes an indication to route future commands and/or data to the secondary ring bus extending from the bus bridge. The bus bridge is configuration to, in response to the configuration command, configure the bus bridge to route future commands and/or data from the primary ring bus to the secondary ring bus.

Systems and methods for managing programming schedules of programming host data and maintenance operations in a non-volatile memory are disclosed. A method includes determining multiple integer interleave ratios of host data writes to relocation writes of previously programmed data when non-integer interleave situations are determined for a previously programmed source block selected for a maintenance operation. The method may include writing the host data and relocating previously programmed data in groups of operations having these determined integer interleave ratios. A memory system may include non-volatile memory and a controller configured to identify non-integer interleave situations and then break up the host data and relocation data writes into multiple interleave groups each having a different integer interleave ratio such that a whole number of write operations for the interleave groups may be carried out to achieve more precise control and efficiency in maintenance operations.

System and method for precision interleaving of data writes in a non-volatile memory

A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Method and system for asynchronous die operations in a non-volatile memory

A multi-layer memory and method for performing background maintenance operations are disclosed. The memory includes a plurality of flash memory die having multiple layers, where each layer is made up of flash memory cells having a greater bit per cell storage capacity than then prior layer and each layer may have a plurality of partitions for different data types. A controller managing the flash memory die is configured to identify an idle die and determine if a layer in the die satisfies a background maintenance criterion. Upon identifying a layer satisfying the background maintenance criterion, the valid data from reclaim blocks in the layer is relocated into a relocation block in the same layer until the relocation block is filled and the background maintenance cycle ends.

Method and system for managing background operations in a multi-layer memory

A non-volatile memory system may have a group of non-volatile memory cells having a plurality of predetermined portions, where each predetermined portion is associated with an open host write block of a different host data type than each other predetermined portion. A host data router directs received data from a host to an appropriate predetermined portion based on a determined data type. A maintenance data router, based on predetermined minimum capacity overprovisioning targets for each predetermined portion, operates to adjust an amount of overprovisioning of physical capacity among the plurality of predetermined portions to reduce write amplification and increase performance in predetermined portions having data with a higher probability of host update. The method may include selecting a particular predetermined portion and a particular block within the selected predetermined portion on which to perform a maintenance operation to achieve the desired capacity overprovisioning.

System and method for managing data in a memory device

Systems and methods for implementing adaptive memory layers in a storage system are disclosed. A storage system may include a non-volatile memory with memory cells configurable to each of a plurality of bit-per-cell capacities and divided into dynamically re-sizable memory layers defined by memory cells of a particular capacity. A memory layer adjustment module associated with a controller of the storage system is configured to, upon detection of a maintenance trigger, compare the amount of valid data and overprovisioning in each layer to a target amount and to redistribute valid data and physical capacity among the memory layers according to a predetermined table or algorithm in order to optimize performance of each memory layer.

System and method for adaptive memory layers in a memory device

Memory systems having a volatile memory, a non-volatile memory arranged in blocks, and a controller coupled to the volatile memory and to the non-volatile memory. The controller is configured to maintain, in the volatile memory, a list of addresses of erased blocks of the non-volatile memory. The list of addresses of erased blocks of the non-volatile memory is limited to a maximum number of list entries. The controller is further configured to transfer the list of addresses of erased blocks of the non-volatile memory from the volatile memory to the non-volatile memory in response to the list containing its maximum number of list entries and/or in response to an operation that would increase the number of list entries to a number equal to or greater than the maximum number of list entries.

Memory systems

A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than the prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met.

Growing community of inventors

Falkirk, United Kingdom

Alan Welsh Sinclair