International Business Machines Corporation

Alan Weger

Franco Stellari

Peilin Song

Stanislav Polonsky

Dzmitry S Maliuk

Hendrik F Hamann

Keith Aelwyn Jenkins

Barry P Linder

Herschel Akiba Ainspan

Emmanuel Yashchin

Seongwon Kim

Raphael Peter Robertazzi

James H Stathis

Emily A Ray

Kevin Geoffrey Stawiasz

James Andrew Lacey

Chandler Todd McDowell

Jamil A Wakil

Tian Xia

Steven H Voldman

Pradip Bose

Hubertus Franke

Eren Kursun

Robert J Von Gutfeld

Jeanne P Bickford

Chen-Yong Cher

Martin Patrick O'Boyle

Kerry A Kravec

Wing L Lai

Sebnem Jaji

Andrea Bahgat Shehata

Brian M Trapp

Thomas S Barnett

Naoko Pia Sanda

Rashmi D Chatty

Stephen Bradley Ippolito

Gie Lee

William Y Chang

Moyra K Mc Manus

Methods and systems of detecting chip degradation are described. A processor may execute a test on a device at a first time, where the test includes executable instructions for the device to execute a task under specific conditions relating to a performance attribute. The processor may receive performance data indicating a set of outcomes from the task executed by the device during the test. The processor may determine a first value of a parameter of the performance attribute based on the identified subset. The processor may compare the first value with a second value of the parameter of the performance attribute. The second value is based on an execution of the test on the device at a second time. The processor may determine a degradation status of the device based on the comparison of the first value with the second value.

Detection of performance degradation in integrated circuits

A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.

Scan chain latch design that improves testability of integrated circuits

A method and system are provided for chip testing. The method includes selectively deploying a chip for future use or discarding the chip to prevent the future use, responsive to a stress history of the chip determined using a non-destructive test procedure. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto. The test procedure further includes ranking each of the plurality of patterns based on at least one preceding available pattern to provide a plurality of pattern ranks. The test procedure also includes calculating a sum by summing the plurality of pattern ranks. The sum calculated during an initial performance of the test procedure is designated as a baseline, and the sum calculated during a subsequent performance of the test procedure is compared to a threshold derived from the baseline to determine the stress history of the chip.

Non-destructive analysis to determine use history of processor

A computer-implemented device and method for identifying hardware Trojans and defects based on light emissions from Integrated Circuits (ICs) is provided. A measured emissions map is received based on light emissions captured from a sacrificial test IC. The sacrificial test IC is a partially manufactured IC fabricated to include a set of frontend layers of an IC architecture but not a set of backend layers of the IC architecture. The sacrificial test IC also includes a sacrificial layer for powering devices in the partially manufactured IC without the set of backend layers. An expected emissions map is derived from the sacrificial test IC and the measured emissions map is compared with the expected emissions map to identify deviations from the IC architecture in the frontend layers.

Detection of hardware trojan using light emissions with sacrificial mask

A method and system are provided for chip testing. The method includes ascertaining a baseline for a functioning chip with no stress history by performing a non-destructive test procedure on the functioning chip. The method further includes repeating the test procedure on a chip under test using a threshold derived from the baseline as a reference point to determine a stress history of the chip under test. The test procedure includes ordering each of a plurality of functional patterns by a respective minimum operating period corresponding thereto, ranking each pattern based on at least one preceding available pattern to provide a plurality of pattern ranks, and calculating a sum by summing the pattern ranks. The sum calculated by the ascertaining step is designated as the baseline, and the sum calculated by the repeating step is compared to the threshold to determine the stress history of the chip under test.

Methods for testing the resolution of an imaging device include forming a plurality of semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size. The semiconductor devices are activated by providing an input signal. Light emissions from one or more of the activated semiconductor devices are suppressed by providing one or more select signals.

Minimum-spacing circuit design and layout for PICA

PICA test methods are shown that includes forming semiconductor devices having proximal light emitting regions, such that the light emitting regions are grouped into distinct shapes separated by a distance governed by a target resolution size; forming logic circuits to control the semiconductor devices; activating the one or more semiconductor devices by providing an input signal; and suppressing light emissions from one or more of the activated semiconductor devices by providing one or more select signals to the logic circuits.

PICA test circuits are shown that include a first transistor and a second transistor laid out drain-to-drain, such that a gap between respective drain regions of the first and second transistors has a minimum size allowed by a given fabrication technology.

A semiconductor wafer resting on a contact element has a spatially distributed force applied to its frontside and an equal and opposing force applied to its backside. The contact element comprises a solid immersion lens (SIL), and has an area less than the area of the wafer, but no less than the larger of the area of an optical collection area and an electrical probe assembly. The equal and opposing forces cause the wafer to conform to the shape of the contact element. Measurements, including electrical testing, optical probing and wafer characterization are performed on the wafer.

Method and apparatus for probing a wafer

Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.

Constructing variability maps by correlating off-state leakage emission images to layout information

A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task execution is monitored for hot tasks and especially for hotspots. Task execution is balanced, thermally, to minimize hot spots. Thermal balancing may include Simultaneous MultiThreading (SMT) heat balancing, chip-level multiprocessors (CMP) heat balancing, deferring execution of identified hot tasks, migrating identified hot tasks from a current core to a colder core, User-specified Core-hopping, and SMT hardware threading.

Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management

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Mohegan Lake, NY, United States of America

Alan Weger