Sun Microsystems, Inc.

Silicon Image Gmbh

Lattice Semiconductor Corporation

Keyssa Systems, Inc.

Alan T Ruberg

James Gregory Hanko

Roger Dwain Isaac

J Duane Northcutt

Lawrence Llewelyn Butcher

Gerard A Wall

Dongyun Lee

Srikanth Gondi

Daeyun Shim

Sungjoon Kim

John C Tang

Trevor Morris

Thomas K Rodriguez

Ellen Isaacs

Rick Levenson

Hyung Rok Lee

Anu Murthy

Duane Northcutt

Sunderraj V Palaniraj

Myung Rai Cho

Hoo Kim

Eswar Priyadarshan

Jerry Wall

Arvind Srinivasan

Brian Keith Schmidt

Sami Shaio

Edward T Pak

Neil C Wilhelm

Benjamin H Stoltz

Dae Kim

Marc Whitney Schneider

Seung-Jong Lee

Jeff Cuppett

Timothy Shea

Manpop A Lau

Seung-jong Lee

Seoung Jeong Lee

Ruthellen Leventer

Neil Katin

Heather A McIntosh

Satyanarayana Simha

Michael E Duboce

Herbert Bos

A universal protocol engine circuit aggregates data of multiple communication ports that may use different communication protocols according to a configurable communication protocol. In a transmitter mode, the universal protocol engine circuit references a slot table defining a sequence of the ports to generate output data from the input data received from the ports, and transmits the output data over a wired or wireless communication link. In a receiver mode, the universal protocol engine circuit references the slot table to parse input data from the communication link into output data for each of the ports. The sequence of ports of the slot table may be configurable according to the speed or other properties of the communication ports.

Virtual pipe for connecting devices

Embodiments discussed herein refer to systems, methods, and circuits for conforming to power up sequencing rules of a conventional hard-wired data connection even though the hard-wired data connection that would ordinarily exist between two data controllers has been replaced with one or more contactless connectors. A consequence of replacing the hard-wired connection with a contactless connector is that the data controllers no longer directly control the power sequencing between the controllers because they are not able to directly communicate with each other over the hard-wired data connections. Power sequence assist circuitry may be used to assists the data controllers in establishing a link in accordance with the power sequencing rules of a particular wired interface despite the intentionally broken hard-wired data connection between the two controllers by instructing the contactless connectors to communicate with their respective data controllers in compliance with the power sequencing rules.

Power sequencing circuitry and methods for systems using contactless communication units

A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.

Method and system for improving serial port memory communication latency and reliability

A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.

Calibration of single-ended high-speed interfaces

Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

Single-ended configurable multi-mode driver

A mechanism for facilitating improved refresh schemes for memory devices is described. In one embodiment, an apparatus includes a memory device having refresh logic and memory cells, the memory cells including data cells and supplemental cells, the supplemental cells to be observed. The supplemental cells emulate a decay characteristic of the data cells performing regular refresh operations according to an existing refresh policy. The apparatus may further include the refresh logic to receive, from the supplemental cells, observation data relating to decaying of the supplemental cells, and correlate the observation data to data cell performance. The refresh logic to generate a policy recommendation based on the observation data collected by the supplemental cells.

Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices

Single ended configurable multi-mode driver

Embodiments of the invention are generally directed to a hybrid interface for serial and parallel communication. An embodiment of a method includes initializing a first apparatus for transmission of data to or reception of data from a second apparatus, switching an interface for the first apparatus to a first mode for a parallel interface, the parallel interface including a first plurality of pins, and transmitting or receiving parallel data in the first mode via the first plurality of pins. The method further includes switching the interface of the first apparatus to a second mode for a serial interface, the serial interface including a second plurality of pins, the first plurality of pins and the second plurality of pins both including an overlapping set of pins, and transmitting or receiving serial data in the second mode via the second plurality of pins.

Hybrid interface for serial and parallel communication

A method and system for inter-port communication utilizing a multi-port memory device. The memory device contains an interrupt register, an interrupt signal interface (e.g., a dedicated pin), an interrupt mask, and one or more message buffers associated with each port. When a first component coupled to a first port of the memory device wants to communicate with a second component coupled to a second port of the memory device, the first component writes a message to a message buffer associated with the second port. An interrupt in the input register of the second port is set to notify the second component coupled to the second port that a new message is available. Upon receiving the interrupt, the second component reads the interrupt register to determine the nature of the interrupt. The second component then reads the message from the message buffer.

Inter-port communication in a multi-port memory device

A method and system that utilizes a shared nonvolatile memory for initializing multiple processing components in a device. The startup logic and configuration data for processing components within a device is stored in a single nonvolatile memory. Upon receipt of a command to initialize the device, the shared memory system copies the startup logic and configuration data from the nonvolatile memory to a volatile main memory. Then, each processing component accesses the main memory to find its startup logic and configuration data and begin executing. The shared memory system reduces the number of nonvolatile memory components used to initialize multiple processing components.

Shared nonvolatile memory architecture

Growing community of inventors

Menlo Park, CA, United States of America

Alan T Ruberg