Sun Microsystems, Inc.

Oracle International Corporation

Alan Smith

Robert Paul Masleid

Ali Vahidsafa

Toshinari Takayanagi

Georgios K Konstadinidis

Massimo Sutera

Yibin Xia

Senthilkumar Diraviam

Mohd Jamil Mohd

Ming Yin

Kevin J Wu

Harry Ma

George K Konstadinidis

Dinesh Rajasavari Amirtharaj

Systems, methods, and other embodiments associated with providing a unified tool for performing design constraints generation and verification for circuit designs are described. In one embodiment, the unified tool reads design data and design intent information for a circuit design. The unified tool generates physical flow elements and verification flow elements of the circuit design, together and in dependence on each other, based, at least in part, on the design data and the design intent information.

Unified tool for automatic design constraints generation and verification

A method for determining flop circuit types includes performing a layout of an IC design including arranging master and slave latches of each of a plurality of flops to receive first and second clock signals, respectively. The initial IC design may then be implemented (e.g., on a silicon substrate). After implementation, the IC may be operated in first and second modes. In the first mode, the master latch of each flop is coupled to receive a first clock signal. In the second mode, the first clock signal is inhibited and the master latch is held transparent. The slave latch of each flop operates according to a second clock signal in both the first and second modes. The method further includes determining, for each flop, whether that flop is to operate as a master-slave flip-flop or as a pulse flop in a subsequent revision of the IC.

Flop type selection for very large scale integrated circuits

A method is provided for modeling timing characteristics of a circuit block of an integrated circuit, which includes a main circuit and a timing circuit. The method comprises determining an output pin output delay and determining a timing circuit delay. The output pin output delay is an interval of time from a clock signal reaching a clock reference point (CRP) to an output signal arriving at the output pin. The clock reference point is positioned between the timing circuit and the main circuit. The timing circuit delay is an interval of time from a clock signal arriving at a clock input pin to a clock signal arriving at the CRP. The determination of the timing circuit delay is based on a computer simulation of a netlist of circuit elements in the timing circuit.

Method and system for timing modeling for custom circuit blocks

A method for minimizing noise in an integrated circuit is described, the method including choosing a net to be analyzed, determining that the total path length of conductive paths coupled to a driver within the net exceed a maximum acceptable length for that given driver according to the minimum acceptable noise levels for that given net, and inserting at least one buffer within the net at a position which is within the maximum acceptable length for conductive paths coupled to the driver.

Method for reducing noise in integrated circuit layouts

Performance of an integrated circuit design, whether embodied as a design encoding or as a fabricated integrated circuit, can be improved by selectively substituting low V transistors in a way that prioritizes substitution opportunities based on multi-path timing analysis and evaluates such opportunities based on one or more substitution constraints. By valuing, in a prioritization of substitution opportunities, contributions for all or substantially all timing paths through the substitution opportunity that violate a max-time constraint, repeated passes through a timing analysis phase can be advantageously avoided or limited. In addition, by recognizing one or more constraints on actual low V substitutions, particular noise-oriented constraints, the scope of post substitution design analysis can be greatly reduced. In some realizations, substitutions are performed so long as a leakage current budget is not expended. As a result, integrated circuit designs prepared in accordance with the described techniques may exhibit substantial cycle time improvements through judicious selection of gate instances for substitution. In some realizations, improved yields of high grade parts may result.

Low Vt transistor substitution in a semiconductor device

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Santa Clara, CA, United States of America

Alan Smith