Texas Instruments Corporation

Alan Scott Hearn

Jeffrey Matthew Kempf

Donald B Doherty

Jeffrey Scott Farris

William J Sexton

Larry R Hite

Virgilio N Garcia

Steven E Sparks

A word data loading circuit for a spatial light modulator includes a shadow load register (SLR), a load controller, and a word pattern generation (WPG) circuit. The SLR loads a first word of a pseudorandom image pattern. The load controller parallel shifts the first word to a memory cell array. The WPG circuit generates a next word and controls the SLR to change the first word to the next word. The load controller parallel shifts the next word to the array. The WPG circuit generates an additional word and controls the SLR to change the next word to the additional word. The load controller parallel shifts the additional word to the array. The WPG circuit, SLR, and load controller generate and parallel shift further additional words to the array until the pseudorandom image pattern is loaded in the array.

Spatial light modulator with embedded pattern generation

In accordance with the teachings of the present invention, a system and method for optimizing DRAM refreshes in a multi-channel memory controller are provided. In a particular embodiment, the method includes receiving, at a router in a light modulation system, a signal from one of a plurality of channels operable to read or write to a plurality of DRAM banks, the signal indicating that the channel does not need to access the plurality of DRAM banks during predetermined time period. The method also includes indicating the receipt of the signal to a refresh channel including a plurality of counters, wherein each counter is operable to track refreshes of a respective one of the plurality of DRAM banks. The method further includes receiving, from the refresh channel, an indication of one of the plurality of DRAM banks to refresh in response to the receipt of the signal, and refreshing the indicated DRAM bank.

System and method for optimizing DRAM refreshes in a multi-channel memory controller

An image compression and decompression method compresses data based upon the data states, and decompresses the compressed data based upon the codes generated during the compression.

Circuit and method for adaptive, lossless compression of successive digital data

Disclosed embodiments reveal techniques for efficiently allocating time slots in a time-division multiplex (TDM) cycle among multiple channels of varying size, particularly when the channels do not all desire an integer number of time slots. TDM cycles can only allocate an integer number of time slots to each channel. So when at least one channel does not desire an integer number of time slots, then the disclosed embodiments allocate a number of time slots equal to the integer portion to each channel, rolling any fractional remainder over to the next cycle. This cumulative cyclical fractional summing process efficiently allocates time slots among the channels, allowing the average allocation per cycle to approach the true non-integer desired amount over time.

Time-division multiplex arbitration with fractional allocation

A method of addressing double buffered memory for an SLM, the memory address having only two bank bits. It is assumed that the pixel data is formatted into bit-planes, such that pixel positions in each bit plane can be identified. A bit plane bit is mapped to a first bank bit, and a pixel position bit is mapped to a second bank bit. The read/write bit is mapped to a column address bit. The remaining bit plane and pixel position bits are mapped to row address and column address bits.

SLM display data address mapping for four bank frame buffer

A programmable burst FIFO buffer ( ) allows for burst of data to be loaded into memory ( ) without the device writing into the buffer having to check on every clock cycle as to whether the buffer is full or not. The buffer ( ) is also programmable and allows for &ldquo;N&rdquo; words to be loaded with &ldquo;N&rdquo; being programmable in any given burst without having to check for a buffer full condition. The buffer ( ) also avoids the glitches associated with other buffer designs due to the write and read clock being in different domains.

Programmable burst FIFO

Circuits, systems, and methods, relating to a controllably switched phase locked loop. The system indudes a phase locked loop circuit (16) having a clock signal input (16c), a clock signal lock input (16a), and a clock adjustment signal input (16b). The system further includes circuitry (12c) for coupling a clock signal to the clock signal input, circuitry (28) for coupling a first clock adjustment signal to the clock adjustment signal input, and circuitry (24) for comparing the first clock adjustment signal to a second clock adjustment signal. Lastly, the system includes circuitry responsive to the comparing circuitry. This responsive circuitry includes firstly, circuitry (26) for coupling a signal to the clock signal lock input such that the phase locked loop circuit indicates an unlocked state, and secondly circuitry (22, 28) for coupling the second clock adjustment signal to the clock adjustment signal input after the phase locked loop circuit indicates an unlocked state.

Controllably switched phase locked loop circuits, systems, and methods

A GaAs register for storing of digital data is configured with a plurality of 'D' type flip-flops having a data terminal and an enable terminal connected to an enabled GaAs clock circuit. The enabled GaAs clock circuit provides a load clock signal to enable the 'D' type flip-flops during the loading of data into the plurality of 'D' type flip-flops and to prohibit the loading of data without the load clock signal. The enabled GaAs clock circuit has 'D' type flip-flop, a clock input circuit and a combining circuit. The clock input circuit receives a clock signal and delays the clock signal. The 'D' type flip-flop loads the load enable signal with the rising edge of the clock signal and the delayed clock signal and the loaded enable signal are combined to obtained a combination signal which is used to load data into the plurality of 'D' type flip-flops in the register.

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Allen, TX, United States of America

Alan Scott Hearn