Agere Systems Inc.

Triquint Semiconductor Corporation

Qorvo Us, Inc.

Lucent Technologies Inc.

Agere Systems Guardian Corp.

Alan Sangone Chen

Daniel Charles Kerr

Kurt George Steiner

Nace Rossi

Mark Dyson

Benjamin P Abbott

William A Russell

Ranbir Singh

Taeho Kook

Yih-Feng Chyan

Robert Aigner

Samir Chaudhry

Daniel Patrick Chesire

Michael Scott Carroll

Amal Ma Hamad

Edward Paul Martin, Jr

Julien Gratier

Jean Briot

Suzanne Combe

Timothy Daniel

William John Nagy

Xiaojun Yuan

Roscoe T Luce

Curtiss Hella

Michele Marie Jamison

Kevin J Gamble

Chad Thompson

Yi Ma

Kuo-Hua Lee

Marc Solal

David W Kelly

Chung Wai Leung

Seungmoo Choi

George Grama

Natalya F Naumenko

Ian Y Yee

Stephen Carl Kuehne

Charles E Carpenter

Tony G Ivanov

Roger W Key

Daniel J Dolan, Jr

Donald Thomas Cwynar

Timothy Edward Doyle

Bradley J Albers

Stephen A Neston

Robert W Dail

Troy A Giniecki

Scott Shive

Reduced-size guided-surface acoustic wave (SAW) resonators are disclosed. Guided-SAW resonators can achieve high acoustic coupling and acoustic quality Q, but may have a larger surface area compared with a traditional temperature compensated (TC)-SAW resonator. In an exemplary aspect, a guided-SAW device is fabricated with a metal-insulator-metal (MIM) capacitor to produce a guided-SAW which has the same high Q with a surface area which is the same or less than traditional TC-SAW resonators.

Reduced-size guided-surface acoustic wave (SAW) devices

Acoustic filtering circuitry includes a piezoelectric layer, a dielectric layer, a plurality of acoustic resonators, and a capacitor. The dielectric layer is over a surface of the piezoelectric layer. The plurality of acoustic resonators each includes a transducer on the surface of the piezoelectric layer such that the transducer is between the piezoelectric layer and the dielectric layer. The capacitor includes a first plate on the surface of the piezoelectric layer such that the first plate is between the piezoelectric layer and the dielectric layer and a second plate over the first plate such that the second plate and the first plate are separated by at least a portion of the dielectric layer.

Acoustic filtering circuitry including capacitor

An acoustic wave device includes a piezoelectric layer, an interdigital transducer, and a slow wave propagation overlay over a portion of the interdigital transducer. By providing electrode fingers of the interdigital transducer such that a portion of the width thereof is dependent on an electrode period, a desirable wave mode may be maintained in the acoustic wave device. Further, by varying a width of the slow wave propagation overlay based on the electrode period, the desirable wave mode may be further maintained.

Guided acoustic wave device

Embodiments of a Surface Acoustic Wave (SAW) device, or filter, and methods of fabrication thereof are disclosed. In some embodiments, the SAW filter comprises a piezoelectric substrate and an Interdigitated Transducer (IDT) on a surface of the piezoelectric substrate. The IDT includes multiple fingers, each comprising a metal stack. The SAW filter further includes a cap layer on a surface of the IDT opposite the piezoelectric substrate and on areas of the surface of the piezoelectric substrate exposed by the IDT. The cap layer has a thickness in a range of and including 10 to 500 Angstroms and a high electrical resistivity (and thus a low electrical conductivity). For instance, in some embodiments, the electrical resistivity of the cap layer is greater than 10 kilo-ohm meters (K&#x3a9;&#xb7;m). The SAW filter further includes an oxide overcoat layer on a surface of the cap layer opposite the IDT and the piezoelectric substrate.

Surface acoustic wave filter with a cap layer for improved reliability

Embodiments described herein may provide a temperature-compensated surface acoustic wave (TCSAW) device, a method of fabricating a TCSAW device, and a system incorporating a TCSAW device. The TCSAW device may include a pyroelectric substrate, a plurality of electrodes formed on a first surface of the pyroelectric substrate, an amorphous silicon layer formed over the plurality of electrodes, and a temperature compensating layer formed over the amorphous silicon layer.

Methods, systems, and apparatuses for temperature compensated surface acoustic wave device

Embodiments described herein may provide an acoustic wave device, a method of fabricating an acoustic wave device, and a system incorporating an acoustic wave device. The acoustic wave device may include a transducer disposed on a substrate, with a contact coupled with the transducer. The acoustic wave device may further include a wall layer and cap that define an enclosed opening around the transducer. A via may be disposed through the cap and wall layer over the contact, and a top metal may be disposed in the via. The top metal may form a pillar in the via and a pad on the cap above the via. The pillar may provide an electrical connection between the pad and the contact. In some embodiments, the acoustic wave device may be formed as a wafer-level package on a substrate wafer.

Acoustic wave device

Disclosed embodiments include a surface acoustic wave device having electrode period, electrode width, and/or ratio of electrode width to electrode period varied in a prescribed manner.

High coupling, low loss saw filter and associated method

An acoustic wave device operable as a piston mode wave guide includes electrodes forming an interdigital transducer on a surface of the piezoelectric substrate, wherein each of the plurality of electrodes is defined as having a transversely extending center region and transversely opposing edge regions for guiding an acoustic wave longitudinally through the transducer. A Silicon Oxide overcoat covers the transducer and a Silicon Nitride layer covers the Silicon Oxide overcoat within only the center and edge regions. The thickness of the Silicon Nitride layer is sufficient for providing a frequency modification to the acoustic wave within the center region and is optimized with a positioning of a Titanium strip within each of the opposing edge regions. The Titanium strip reduces the acoustic wave velocity within the edge regions with the velocity in the edge regions being less than the wave velocity within the transducer center region.

Acoustic wave guide device and method for minimizing trimming effects and piston mode instabilities

The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector that ranges from about 0.9 microns to about 2.0 microns.

Bipolar device having improved capacitance

A SAW device having metal electrodes on a surface of the piezoelectric substrate includes a dielectric layer deposited on the surface. Depositing the layer results in seams extending upward from the electrodes extending above the surface of the substrate. An additional seam results from one seam extending from one electrode joining a second seam extending from an adjacent electrode within the dielectric layer and is generally formed above the height of the electrodes. The additional seam is removed through planarization or the like. The dielectric layer may be further planarized for providing a thickness of the dielectric layer above the electrodes as desired.

Temperature compensated surface acoustic wave device and method having buried interdigital transducers for providing an improved insertion loss and quality factor

The invention, in one aspect, provides a method for fabricating a semiconductor device. In one aspect, the method provides for a dual implantation of a tub of a bipolar transistor. The tub in bipolar region is implanted by implanting the tub through separate implant masks that are also used to implant tubs associated with MOS fabricate different voltage devices in a non-bipolar region during the fabrication of MOS transistors.

Method to reduce collector resistance of a bipolar transistor and integration into a standard CMOS flow

The invention, in one aspect, provides a method for fabricating a semiconductor device, which includes conducting an etch through an opening in an emitter layer to form a cavity from an underlying oxide layer that exposes a doped tub. A first silicon/germanium (SiGe) layer, which has a Ge concentration therein, is formed within the cavity and over the doped tub by adjusting a process parameter to induce a strain in the first SiGe layer. A second SiGe layer is formed over the first SiGe layer, and a capping layer is formed over the second SiGe layer.

Method to improve writer leakage in SiGe bipolar device

The invention, in one aspect, provides a semiconductor device that comprises a collector located in a semiconductor substrate and an isolation region located under the collector, wherein a peak dopant concentration of the isolation region is separated from a peak dopant concentration of the collector by at least about 0.9 microns. The invention also provides a method for forming this device.

An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

Integrated circuit with depletion mode JFET

Method to improve writer leakage in a SiGe bipolar device

Growing community of inventors

Windermere, FL, United States of America

Alan Sangone Chen