Texas Instruments Corporation

Alan S Ward

Reid E Tatge

Eric J Stotzer

David Harold Bartley

Jonathan F Humphreys

Elana D Granston

Paul Fuqua

Joseph R Zbiciak

A method of generating profiled optimized code using user interface () that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided. A program () is compiled in a compiler () with two or more compiler options such as size and speed and the resulting executables () are profiled (). The results of the profiles () are analyed in a solver () for generating sets of useful solutions () wherein the sets have methods of compiling at the function level. The useful solutions () are displayed () at the user interface () to allow the user to visually understand, inspect and manipulate compiler options to select compiler options () for the program.

Method of generating profile-optimized code

A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction. Further, a method according to this invention may include the steps of locating delayed effect instructions followed by NOPs, such as load or branch instructions, within a code; deleting the NOPs from the code; and inserting a NOP field into the delayed effect instructions. Apparatus according to this invention may include a processor including a code containing a delayed effect instruction, wherein the delayed effect instruction includes a NOP field.

Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands

A method for reducing a code size of a software pipelined loop, the software pipelined loop having a kernel and an epilog. The method includes first evaluating a stage of the epilog. This includes selecting a stage of the epilog to evaluate ( ) and evaluating an instruction in a reference stage. This includes identifying an instruction in the reference stage that is not present in the selected stage of the epilog ( ) and determining if the identified instruction can be speculated ( ). If the identified instruction can be speculated, such is noted. If the instruction cannot be speculated, it is determined whether the identified instruction can be predicated ( ). If the instruction can be predicated, it is marked as needing predication ( ). Next, it is determined if another instruction in the reference stage is not present in the selected stage of the epilog ( ). If there is, the instruction evaluation is repeated. If there is another stage of the epilog to evaluate, the evaluation is repeated ( ).

Method for collapsing the prolog and epilog of software pipelined loops

A user interface that allows a user to visually understand, inspect, and manipulate a compiled application program as a function of compiler options, such as, code size and speed, is provided.

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Sugar Land, TX, United States of America

Alan S Ward