Adv Antest Corporation

Agilent Technologies, Inc.

Alan S Krech

Olaf Pöppe

Michael Frank Jones

Eric Kushnick

Klaus-Dieter Hilliges

An automated test equipment for testing one or more devices under test, comprises at least one port processing unit, comprising a high-speed-input-output interface, HSIO, for connecting with at least one of the devices under test, a memory for storing data received by the port processing unit from one or more connected devices under test, and a streaming error detection block, configured to detect a command error in the received data, wherein the port processing unit is configured to, in response to detection of the command error, limit the storing in the memory of data following, in the received data, after the command which is detected to be erroneous. A method and computer program for automated testing of one or more devices under test are also described.

Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program for handling command errors

An automated test equipment for testing one or more devices under test comprising a plurality of port processing units, comprising at least a respective buffer memory, and a respective high-speed-input-output, HSIO, interface for connecting with at least one of the devices under test. The port processing units are configured to receive data, store the received data in the respective buffer memory, and provide the data stored in the respective buffer memory to one or more of the connected devices under test via the respective HSIO interface for testing the one or more connected devices under test. A method and computer program for automated testing of one or more devices under test are also described.

Automated test equipment for testing one or more devices under test, method for automated testing of one or more devices under test, and computer program using a buffer memory

A programmable logic device, such as a field programmable gate array (FPGA), is disclosed that allows for both high speed and low speed signal processing using the existing high speed transceiver. The programmable logic of the device may be programmed to include a sampling logic block that determines the low speed bit patterns from a device under test (DUT). The logic may further include a bit replication logic block that replicates bits such that the output of the device's high speed transceiver looks like a low speed signal to the DUT. The device, therefore, can communicate with the DUT at both the high and low speeds without the need for intermediate hardware.

Method and apparatus to provide both high speed and low speed signaling from the high speed transceivers on an field programmable gate array

A circuit and method for efficiently configuring an ACAM Select RAM for an ACAM circuit of a tester that tests multiple devices under test (DUTs).

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Fort Collins, CO, United States of America

Alan S Krech