International Business Machines Corporation

Other

Alan Robert Clark

Glen Alan Jaquette

Robert Allen Hutchins

Ara Sarkis Patapoutian

Pantas Sutardja

Robert Allan Hutchins

James Edward Hughes

Sivarama K Kodukula

James W Valashinas

Joseph P Higham

A replacement heart valve comprising a memory shape element. The various embodiments use internal body heat to seat and retain the valve within a blood passage. The element can be provided in a variety of shapes and sizes, and is at least partially encased within an inert and pliant encasing material. The encasing material is one that is adapted to be contiguous with the structure of the valve nozzle or backflow-resistant leaf structure, and may be used in combination with existing stents or an incorporated stent, including ones having a structure similar to conventional stents.

Memory material valve

An integrated calibration apparatus operates in multiple calibration modes of a multi-mode information storage system such as an optical disk drive to calibrate the drive in the multiple write modes. An event processing and measurement circuit is configurable in multiple configurations that each correspond to a different calibration measurement. Each configuration concurrently measures one or more parameters of readback data written to an optical disk by the optical disk drive operating in a particular write mode. A qualification circuit selects valid measurements for two different parameters or for two different qualification of the same parameter. A summation circuit sums valid measurements of each parameter measured and counts the number of measurements summed for each parameter. The calibration apparatus calculates average values for the measured parameters from the sums and counts, and then calibrates the multi-mode optical disk drive for its current write mode based on the average values.

Integrated calibration apparatus for a multi-mode information storage

In a first embodiment, a read detection channel includes a tracking threshold circuit for generating a variable threshold signal and a detection circuit, which is configurable in a number of diverse configurations that each correspond to one of the multiple diverse data formats. In addition, the first embodiment of the read detection channel includes a configuration circuit that automatically selects one of the configurations of the data detection circuit in response to a detection of a format of the input data stream. The first embodiment of the read detection channel permits data bits encoded in multiple diverse data formats to be decoded utilizing a single configurable read detection channel. In a second embodiment, the configurable read detection channel includes a tracking threshold circuit that can be configured to generate a threshold output signal in response to an input signal or in response to the input signal and a phase error signal. The second embodiment of the read detection channel further includes a detection circuit, which indicates data bits detected within the input signal in response to the threshold output signal, and at least one phase-locked loop coupled to the detection circuit, which places each detected data bit within one of a plurality of bit cells within an output data stream. The phase-locked loop also generates a phase error signal that can be selectively coupled to the tracking threshold circuit.

Configurable read detection channel and method for decoding data stored

A programmable writing system for an optical disk drive which is adaptable for pulse position modulation (PPM) and pulse width modulation (PWM) pulse generation. The writing circuit is responsive to a PPM/PWM mode command for generating programmed laser pulse signals. Specifically, a pattern detector is responsive to the PPM/PWM mode command for detecting input data. The detected data is provided to a pulse selector for selecting programmed pulse power and/or duration values, which operate a pulse generator to set pulse power levels and/or to set the duration of the generated laser pulse signals. In PWM mode, the pattern detector provides a toggle signal with each detected signal and the pulse selector responds to the toggle signal to alternate between providing mark pulse power and/or duration values and providing space duration values to thereby provide alternating mark and space signals.

Programmable PPM/PWM writing system for optical disk

In a pulse width modulated read signal channel for an optical disk drive, a data-transition threshold is maintained for data detection by a threshold tracking circuit that estimates the amplitude centerline data-transition threshold from the most recent maximum and minimum values of the read signal waveform. To improve the accuracy of the response of the centerline estimator, the threshold is increased or decreased based on the phase error at each read signal transition through the data-transition threshold. In addition, defects in the optical recording media are detected, and a defect present signal is used to inhibit the transition phase error input to the centerline estimator. This prevents the estimator from moving the threshold to an incorrect stable level. In addition, the defect present signal boosts the error feedback in the centerline estimator. The estimator then more quickly follows the read signal waveform. As a result, the estimator reacquires the centerline of the waveform after the read head moves past the defect without retriggering the defect detection circuit.

Data-transition threshold following in optical recording

A programmable I/O bus adapter for interfacing and controlling two data processing systems having dissimilar and incompatible architectures. The programmable I/O bus adapter is capable of controlling the I/O bus and adapters of each of the two data processing systems. Simultaneously, the I/O bus adapter provides for interfacing and communication between the two dissimilar data processing systems. Interfacing from the bus adapter to each data processing system is provided by circuitry provided on integrated circuit chip sets specifically designed to interface with each system. The interfacing circuitry is enabled to convert signals between each system to allow for communication. Communication paths couple the adapter to the I/O bus of each system. The ability to access and control an I/O bus and adapter of each system is provided by a microprocessor having microcode instructions stored in programmable memory. The microcode provides for self-contained operation of the I/O bus adapter by enabling it to independently perform I/O control functions of the coupled systems. The microprocessor may be implemented by using a RISC architecture microprocessor device.

Programmable unit for controlling and interfacing of I/O busses of

A digital phase lock loop channel is provided for threshold detection of a pulse width modulated binary data stream that has negative and positive transitions defining one binary state of the data stream. A threshold-establishing and transition-detecting network receives this data stream and provides a first output of one polarity corresponding to the detection of a positive transition, a second output of an opposite polarity corresponding to the detection of a negative transition, and a time-of-arrival output corresponding to a positive and a negative transition. A first and a second digital PLL is provided, each PLL having a transition input, a time-of-arrival input, a phase-error input, a phase error output a data-valid output, and a data output. Each PLL has an internal digital phase detector network connected to receive its transition input and its time-of-arrival input, and each PLL is operable to generate the phase error output therefrom. Each PLL has an internal digital loop filter connected to receive the phase error output generated by its phase detector network, and to receive the phase error output that is generated by the other PLL. The output of the loop filter of each PLL is connected to the data-valid and data outputs of its respective PLL.

Dual digital phase locked loop clock channel for optical recording

A bus-to-bus adapter is provided for coupling the input/output bus of a first data processor to the input/output bus of a second and different type of data processor. The adapter enables the transfer of data and messages from the first processor to the second processor and vice versa. The adapter includes a buffer storage unit and control logic for enabling multiple data buffers to be provided for enabling multiple independent data transfer operations to be performed in a concurrent manner. The control logic also includes a mechanism for allowing the reading out of data from a data buffer to begin before such data buffer has received all of its incoming data. The adapter further includes a programmable service time allocation mechanism for limiting message service time relative to data transfer service time and for providing different amounts of data transfer service time for different ones of the multiple data buffers.

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Tucson, AZ, United States of America

Alan Robert Clark