Daimlerchrysler Corporation

Chrysler Group LLC

Alan Richard Ward

Michael D Hesse

Michael Ray Lindsay

Haitao Lin

Mary Joyce

Roger Thomas Douglas

Jesse Mitchell Saier

Madhu B Banerjee

David R DeRain

John R Dombrowski

The present disclosure provides systems for microprocessors to control a transmission power relay output with a latchdown mechanism in the event that either microprocessor decides it is appropriate to de-energize the relay. Advantageously, the present disclosure allows, for example, the transmission control to be performed by an existing dual microprocessor configuration instead of a custom-designed application specific integrated circuit (ASIC). The microprocessor-based software is more easily updated or changed to add functionality. Further, the present disclosure minimizes unique development with respect to electronic transmission control with a less complex design.

Systems for providing an automobile electronic transmission control monitoring unit with a latchdown mechanism

An apparatus for determining the validity of a data signal communicated between two microprocessors by a dual port RAM includes a sender for providing a data signal and an initialization status indicator and a dual port RAM in communication with the sender for receiving the data signal and the initialization status indicator. The RAM has a first location for storing the data signal and a second location for storing the initialization status indicator. The sender performs initialization on the RAM at the beginning of a data transfer cycle which includes a plurality of data transfer from the sender to a receiver. The sender updates the initialization status indicator as the initialization progresses. The receiver reads the initialization status of the RAM from the second location and subsequently reads the data signal from the first location in association with the initialization status of the RAM.

Dual port RAM communication protocol

A multiplexed addressed data bus are provided for transferring data between two microprocessors. The multiplexed address and data bus include a plurality of multiplexed lines for communicating between the two microprocessors. A read/write signal line is also provided for communicating between the two microprocessors for indicating whether a read or a write operation is to be preformed. A chip select line is provided for transitioning to an enable condition during a data transfer cycle. A data strobe line is in communication between the two microprocessors and provides a strobe signal for each sequence of a data transfer cycle.

Method of multiplexed address and data bus

A method includes diagnosing a solenoid circuit to determine if the circuit has begun to degrade. By measuring characteristics associated with the electrical waveform, it is determined if the characteristics of a solenoid circuit are different from the previously measured characteristics of the circuit, or of a known functioning circuit.

System for monitoring solenoid flyback voltage spike

A messaging system for a vehicle is disclosed. The messaging system includes a primary controller for transmitting and receiving information. The primary controller generates an array of data messages. A communication module is connected to the primary controller for receiving and storing the array of data messages in a memory. The communication module includes a sequencing controller for sequencing through the array of data messages and selecting individual data messages for transmission by the communication module. A data bus is connected to the communication module and provides a communication link between at least one additional vehicle node connected to the data bus.

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Troy, MI, United States of America

Alan Richard Ward