Motorola Corporation

Alan Richard Bormann

Jerry D Moench

Ruey J Yu

Taisheng Feng

Donovan L Raatz

Samuel E Alexander

Robert Tapei Yu

William L Martino

A BICMOS output buffer circuit (20) has a voltage converter (21), a reference voltage circuit (28), a driver circuit (24), and a clamping circuit (40). The reference voltage circuit (28) receives a regulated voltage and provides a reference voltage having a low voltage level and a high voltage level. The low voltage level and the high voltage level control the logic high voltage of an output data signal. During a transition from a logic low voltage to a logic high voltage of the output data signal, the output data signal is allowed to overshoot the low voltage level. After the transition is complete, the output data signal settles at the high voltage level. This limits the amount of overshoot of the output data signal. The clamping circuit (40) dampens the oscillations of the output signal.

BICMOS output buffer circuit having overshoot protection

An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the end of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally caused by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors is controlled by controlling the voltage on the gate or base of the transistor which is providing the particular logic state. This control is responsive to the magnitude of the power supply voltage. An impedance which varies in resistance with supply voltage is placed in series between the positive power supply terminal and the gate or base of the output transistors.

Output buffer for improving di/dt

An integrated circuit comprises a chip containing electric circuits in a package with leads. The chip receives power via the leads. The leads have inductance so that when there is a change in current flow (di/dt) through a lead there is a voltage which is developed between the ends of the lead and the chip which can cause the chip to either malfunction or function poorly. The highest di/dt is generally by an output buffer that changes the logic state of its output. The typical output buffer has a pair of driver transistors that provide one of a logic high or logic low. The di/dt generated by these transistors in controlled by controlling the voltage on the gate of the transistor which is providing the particular logic state. This control reduces di/dt from that typically provided at the very beginning of a logic state transition but increases it over that typically provided immediately thereafter for the purpose of optimizing logic state transition speed for a given maximum di/dt. The control of the gate of the driver transistor is modulated by the output voltage itself.

An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the column decoding function. This prevents the bit sense column selection conductor from being affected when an internal column selection clock signal is generated. This results in a substantial savings in power dissipation which would be required if it were necessary to provide circuitry to disable the internal column selection clock generator circuit during an unselected memory cycle.

Low power MOS RAM address decode circuit

A four-IGFET memory cell is utilized as a static (or DC) memory cell rather than as a dynamic memory cell. When the memory cell is in the standby mode an intermediate voltage is applied to a selection conductor coupled to the gates of the gating IGFETS of the memory cell. The intermediate voltage applied to the 'X' selection conductor under standby conditions is slightly in excess of two IGFET threshold voltages, and is sufficient to maintain the stored logical state, yet causes very little power to be dissipated by the memory cell. A full logical '1' level is applied to the selection conductor during either a read operation or a write operation if the memory cell is selected, i.e. is addressed by the decoding circuitry in response to chip select and address inputs of a memory chip incorporating the memory cell. If the memory cell is unselected during a read or write operation, a logical '0' is applied to the selection conductor. A reference voltage circuit is provided on the semiconductor memory chip including an array of the four-IGFET memory cells in a preferred embodiment of the invention. The reference voltage circuit operates so that each row selection conductor, which is coupled to the gating IGFETS of a row of memory cells, is coupled to the reference voltage conductor when the semiconductor chip is unselected by a separate coupling IGFET coupled, respectively, between the reference voltage conductor and each of the selection conductors. Each selection conductor is also coupled to a selection circuit, which couples the selection conductor toward a V.sub.DD power supply voltage if the corresponding row has been selected by the decode circuitry and the chip is 'selected'. However, if the particular row is not selected, then the corresponding selection conductor is coupled by two IGFETS to a ground voltage supply conductor (if the chip is 'selected').

Static storage technique for four transistor IGFET memory cell

An output circuit including a latch circuit and a push-pull output driver driven by the latch circuit is controlled by disable circuit which disables the output circuit when a random access memory semiconductor chip on which the output circuit is located undergoes an unselected memory cycle, i.e., is unselected. The disable circuit includes a bootstrap NOR gate having a series power switching IGFET coupling its load device to a voltage supply conductor. The power switching IGFET is controlled by the output of the disable circuit so that the disable circuit shuts off its own power at the same time it disables the output latch when the random access memory chip undergoes an unselected memory cycle. Essentially, the disable circuit operates in such a manner that it shuts off its own power and also disables the output circuit in response to a second input signal, conditioned on the occurrence of an earlier first signal.

Low power output disable circuit for random access memory

A decoder for a semiconductor MOS random access memory includes a dynamic NOR gate having a first output. The decoder also includes a selection MOSFET for providing a selection signal to a selection conductor connected to a row or column of an array of storage cells of said random access memory. The gate electrode of the selection MOSFET is connected to the output node of the NOR gate. The drain of the selection MOSFET is connected to a signal conductor adapted to having a signal applied thereto which is a function of a read/write signal applied to said random access memory. The source of the selection MOSFET is connected to the selection conductor. A feedback MOSFET is coupled between the output of the dynamic NOR gate and the selection conductor and has its gate electrode controlled by the signal which is a function of the read/write input signal. When the NOR gate is selected by a particular combination of address input variables, its initially precharged output node is discharged to ground. The feedback MOSFET discharges the selection conductor to ground through the feedback MOSFET and the combination of input MOSFETs of the NOR gate which previously discharged the output node thereof. The discharge of the selection conductor occurs when the read selection signal is applied to the gate of the feedback MOSFET.

Select line hold down circuit for MOS memory decoder

A random access memory includes a plurality of one-transistor storage cells. A plurality of sense-write conductors are included, each connected to a plurality of storage cells in a row of storage cells. A plurality of regenerative sense amplifiers are each coupled to two sense-write conductors. A one-transistor dummy storage cell is connected to each sense-write conductor. Read-write circuitry is coupled between a data conductor of the memory chip and a storage node of one of the dummy storage cells of each row of storage cells. The dummy storage cell is selected whenever a storage cell on the opposite side of the regenerative sense amplifier is selected. Charge initially stored in the selected storage cell is redistributed on the opposite sense-write conductor and is subsequently amplified by the sense amplifier, and produced in inverted amplified form at the storage node of the dummy storage cell. Capacitive loading on all of the sense-write conductors of the memory chip during redistribution of charge in the selected storage cell is thereby reduced, thereby increasing the magnitude of the sense-write conductor voltage transitions when a storage cell is selected.

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Tempe, AZ, United States of America

Alan Richard Bormann