Micron Technology Incorporated

The Perkin-elmer Corporation

Other

Alan R Reinberg

Leonard Forbes

Zhiqiang (Jeff) Wu

Joseph E Geusic

Luan C Tran

Kie Y Ahn

Paul A Farrar

Wendell P Noble

Kirk D Prall

Gurtej S Sandhu

Kunal R Parekh

Randhir P Thakur

Li Li

Kevin G Donohoe

Pai-Hung Pan

Kin F Ma

Tyler A Lowrey

Thomas Arthur Figura

Russell C Zahorik

Arup Bhattacharyya

Randhir P S Thakur

Manny K Ma

Eugene H Cloud

George N Steinberg

Hussein Ibrahim Hanafi

D Mark Durcan

Ceredig Roberts

Mark D Durcan

David J McElroy

Zhigiang (Jeff) Wu

Renee Zahorik, Legal Representative

Howard E Rhodes

Mark E Tuttle

Brian A Vaartstra

J Brett Rolfson

Graham Richard Wolstenholme

Charles B Zarowin

Russell C Zahorik, Deceased

Kevin D Martin

Richard H Bruce

Jean Dalle Ave

David J Mcelroy

Thomas A Figura

Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.

Memory in logic cell

A non-volatile memory device has improved performance from a stressed, silicon nitride capping layer. The device is comprised of memory cells in a substrate that have source and drain regions. A tunnel dielectric is formed over the substrate between each pair of source and drain regions. If the memory device is an NROM, a nitride charge storage layer is formed over the tunnel dielectric. If the memory device is a flash memory, a floating gate is formed over the tunnel dielectric. An inter-gate insulator and control gate are then formed over the charge storage layer. The stressed, silicon nitride capping layer is formed over the control gate.

Non-volatile memory device with tensile strained silicon layer

A structure for storing digital data is provided, with a high reflectance layer comprising a noble metal formed over an underlying material layer, and a plurality of low reflectance portions comprising a mixture of a noble metal and an underlying material. The plurality of low reflectance portions have top surfaces comprising a compound of the underlying and the noble metal. A method of changing reflectance on a data storage disk is also disclosed. The method comprises the acts of irradiating a laser light beam onto a noble metal formed over an underlying layer, and raising the temperature of the noble metal above the melting temperature forming a compound of the noble metal and the underlying material.

Phase change memory for archival data storage

A method and device for cooling an integrated circuit is provided. A method and device using a gas to cool circuit structures such as a number of air bridge structures is provided. A method and device using a boiling liquid to cool circuit structures is provided. Further provided is a method of controlling chip temperature. This allows circuit and device designers an opportunity to design more efficient structures. Some properties that exhibit less variation when temperature ranges are controlled include electromigration, conductivity, operating speed, and reliability.

Integrated circuit cooling and insulating device and method

A memory cell and a method of fabricating the memory cell having a small active area are provided. By forming a spacer in a window that is sized at the photolithographic limit, in one embodiment, a pore may be formed in dielectric layer which is smaller than the photolithographic limit. Electrode material is deposited into the pore, and a layer of structure changing material, such as chalcogenide, is deposited onto the lower electrode, thus creating a memory element having an extremely small and reproducible active area.

Small electrode for a chalcogenide switching device and method for fabricating same

Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Conductive container structures having a dielectric cap

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the &#x3c;110&#x3e; direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure's channel in a (110) plane such that the electrical current flow is in the &#x3c;110&#x3e; direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Method and apparatus on (110) surfaces of silicon structures with conduction in the &#x3c;110&#x3e; direction

A method for forming NMOS and PMOS transistors that includes cutting a substrate along a higher order orientation and fabricating deep sub-micron NMOS and PMOS transistors on the vertical surfaces thereof. The complementary NMOS and PMOS transistors form a CMOS transistor pair. The transistors are preferably used in structures such as memory circuits, e.g., DRAMs, which are, in turn, used in a processor-based system. Ideally, the deep sub-micron NMOS and PMOS transistors are operated in velocity saturation for optimal switching operation.

Method of forming vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, soi and thin film structures

An electrical and thermal contact for use in a semiconductor device. The electrical and thermal contact includes an intermediate conductive layer, an insulator component, and a contact layer. The intermediate conductive layer may contact a structure of the semiconductor device. The insulator component, which is fabricated from a thermally and electrically insulative material, may be sandwiched between the intermediate conductive layer and the contact layer, which may substantially envelop the insulator component. The electrical and thermal contact may be fabricated by a process which includes forming a first thin layer on a surface of the semiconductor device, depositing a dielectric layer adjacent the first thin layer, patterning the dielectric layer to define the insulator component, forming a second thin layer adjacent the insulator component and in partial contact with the first thin layer, and patterning the first and second thin layers to define the intermediate conductive layer and the contact layer, respectively. Due to its structure, which requires relatively little electrical current to generate a desired amount of heat, the electrical and thermal contact effectively contains heat within and prevents heat from dissipating from a contacted structure, and is particularly useful for contacting and inducing a change in the electrical conductivity of structures which include phase change materials.

Electrical and thermal contact for use in semiconductor devices

A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Conductive material patterning methods

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Westport, CT, United States of America

Alan R Reinberg