Advanced Micro Devices Corporation

Dsp Group Limited

Legerity, Inc.

Alan R Hendrickson

Paul G Schnizlein

Peter E Sheldon

Dale E Gulick

Jacqueline E Mullins

A reset circuit that incorporates a battery monitor and watchdog timer in an integrated circuit is disclosed. A battery monitor having an output indicative of a charge state of a battery and a watchdog timer having an output indicative of an operational state of software being executed by the integrated circuit are connected to reset logic having a reset signal output, wherein the reset logic generates a reset signal on the reset signal output if either the battery monitor output or the watchdog timer output is active.

Integrated circuit reset incorporating battery monitor and watchdog timer

A digital cordless telecommunications unit that serves for communications when paired with a similar unit and connected with a network is disclosed. The unit receives analog receive voice signals and transmits analog transmit voice signals. In addition, the unit transmits digital baseband transmit signals and receives digital formatted baseband receive signals. The unit includes a baseband chip, as well as an audio functions circuit and a system control functions circuit. The audio functions circuit comprises an audio front end for receiving the analog receive voice signals and transmitting the analog transmit voice signals, and an adaptive differential pulse code modulator codec, connected to the audio front end, for converting the analog receive voice signals to the digital transmit signals and converting the digital formatted baseband receive signals to the analog transmit voice signals. The system control functions circuit comprises a microcontroller, connected to the codec, for controlling the baseband chip, a memory accessible by the microcontroller for storing control instructions, an interrupt controller connected to the microcontroller, a parallel port connected to the interrupt controller, a wake-up timer connected to the interrupt controller, a clock generator connected to the microcontroller, and a synchronous serial port connected to the interrupt controller.

Narrowband digital cordless telephone

A battery monitor with programmable voltage references. The battery monitor includes a comparator circuit connected to a battery for receiving a voltage level thereof and to a voltage reference circuit for receiving a at least one reference voltage generated thereby. A trim circuit is connected to the voltage reference circuit for adjusting the reference voltage(s) and generated by the voltage reference circuit. The comparator circuit compares the voltage level of the battery with the reference voltage(s) generates an output based on the relative value of the battery voltage compared to the reference voltage(s). The trim circuit is programmable and includes a microprocessor connected to a programmable register and a memory. The microprocessor obtains trim data from the memory and writes the trim data to the programmable register.

Battery monitor with software trim

A method for handling underflow and overflow of data in a FIFO buffer includes steps of inserting an insert data word in the FIFO buffer if there is an underflow of data at the FIFO buffer and discarding a discard data word of the FIFO buffer if there is an overflow of data at the FIFO buffer. In one embodiment, the insert data word is null and does not change the status of the FIFO buffer.

FIFO and system synchronization system and method

A digital communications DQPSK passband detector having a matched filter, a differential decoder, and a slicer that use elementary circuit components. In the matched filter, recovered carrier reference signals are fed along with the received signal to a pair of XNOR gates. This arrangement effectively results in a multiplication operation without any complex circuit elements. The outputs of the XNOR gates control the direction of counting of a pair of binary counters that generate correlated values of the I and Q components in the received signal. Thus, the integrate/dump circuits of a conventional matched filter are replaced with simpler digital counters. A digital differential decoder to extract the phase difference information between two consecutive received symbols is built from a network of delay elements, multipliers, and adders to recover the phase data. The digital differential decoder produces a digital complex-signal output that can be quantized in a digital slicer to decode the plurality of binary bits transmitted through the data symbols. All these operations are performed on digital signals with basic digital circuit elements, thus resulting in a repeatable robust receiver design without complex hardware components.

Passband DQPSK detector for a digital communications receiver

A telephone for digital cordless telecommunications includes a frame formatter for logical channel formatting of transmitted baseband signals and received baseband signals. The telephone comprises a radio interface connection with the frame formatter, a FIFO/codec interface conductively coupled to the frame formatter, an interrupt interface conductively coupled to the frame formatter, a data control logic interface conductively coupled to the frame formatter, and a microcontroller interface conductively coupled to the frame formatter.

Apparatus and method for protocol interface

In a digital communication system for voice signals, a system and method for improving the quality of a received signal. The invention comprises a system for arranging the data and parity bits in a data frame and a corresponding method for analyzing and using the received frames. In the present invention, the data are conveyed in short independent segments, such as one or a few ADPCM nibbles. The length of each segment is chosen to be short enough that the loss of one segment of data from the received signal does not significantly degrade the quality of the output analog signal. The transmitter generates a parity bit for each of these segments and composes transmit frames by alternating data segments with their corresponding parity bits. The receiver then receives each data segment along with its corresponding parity bit. This arrangement allows the receiver to identify specific received segments that contain errors, and minimizes the receiver's delay between receiving the segment and determining if contains an error. The invention also comprises a system and method for detecting such an erroneous segment and blanking it. If a received frame contains more than a threshold number of erroneous segments, then the remaining segments of the frame can be muted. Subsequent frames can then also be muted until one of the subsequent frames contains fewer than a second threshold number of errors.

Parity checking in a real-time digital communications system

A method for enabling communications between a first communications unit and a second communications unit. The first communications unit has a first crystal that provides first unit timing for that unit. The second communications unit has a second crystal that provides second unit timing for the second communications unit. The method includes the steps of receiving the first unit timing by the second communications unit, detecting a transition of a cycle of the first unit timing received, generating a reset pulse upon each detection of the transition of the cycle of the first timing unit received, and initiating a start-up of a new sequence of the second unit timing upon occurrence of the reset pulse. Operation according to the method allows for a wide variety of external protocols to be used with appropriate communications results.

External protocol hooks system and method

Golf club head with a center striking area indicator

A keypad monitor implemented in an integrated circuit monitors the closure of a plurality of keypad switches coupled to input terminals of the integrated circuit. The keypad monitor is operative in a first mode for monitoring a first number of the input terminals and a second mode for monitoring a lesser number of input terminals. When in the second mode, the unmonitored input terminals are converted for a use not related to keypad monitoring.

Programmable keypad monitor

A keypad status reporting system provides an indication over a serial bus as to which switch of a plurality of keypad switches is being selected by an operator wherein each keypad switch is coupled between a respective different pair of row and column conductors. The system generates parallel three-bit row and column addresses, combines the row and column addresses to form a parallel six-bit key code, and converts the key code to serial bits of data and places the serial bits of data onto a multiplexed bus in a predetermined channel.

Growing community of inventors

both of, TX, United States of America

Alan R Hendrickson