Cypress Semiconductor Corporation

Alan R Hawse

Greg J Landry

Risto Bell

James Daniel Merchant

Dragomir Nikolic

Jarrod V Brooks

A design tool, comprising a pattern injection tool configured to automatically allow for the inclusion of dummy structures, differential feature sizing and/or serif addition into integrated circuit (IC) designs, in a pre-processing stage.

Method and apparatus for automated design of integrated circuits

A method of converting or translating a layout or schematic netlist to a simulation netlist, comprising the steps of identifying net-shorting elements in the layout or schematic netlist and automatically replacing at least one such net-shorting element with an RC network to generate the simulation netlist.

METHODS OF CONVERTING AND/OR TRANSLATING A LAYOUT OR CIRCUIT SCHEMATIC OR NETLIST THEREOF TO A SIMULATION SCHEMATIC OR NETLIST, AND/OR OF SIMULATING FUNCTION(S) AND/OR PERFORMANCE CHARACTERISTIC(S) OF A CIRCUIT

Growing community of inventors

Georgetown, KY, United States of America

Alan R Hawse