Intel Corporation

Infineon Technologies Ag

Infineon Technologies Austria Ag

Alan Paussa

Francesco Conzatti

Franz Kuttner

Daniel Gruber

Edwin Thaller

Michael Kalcher

Davide Ponton

Marc Kanzian

Joseph Semmler

Rocco Calabro

This disclosure describes analog to digital converter (ADC) circuitry configured to receive either a differential input signal or a single-ended (SE) input signal and output a digital representation of the input signal using the full-scale of the ADC output. The ADC circuitry of this disclosure includes a true differential ADC that, when receiving a SE input signal is configured to make two adjustments to the ADC characteristic. One adjustment is to shift the ADC characteristic by the reference voltage of the ADC, e.g., Varef. The second adjustment is to multiply the input signal by two, e.g., to double the input signal magnitude.

Single ended conversions on a true differential analog to digital converter (ADC)

In accordance with an embodiment, a method for operating a successive approximation ADC comprising a first capacitor array includes measuring a first weight of an MSB-abit of the ADC by applying a first reference voltage to first terminals of capacitors of the first capacitor array corresponding to the MSB-abit, applying a second reference voltage to first terminals of capacitors of the first capacitor array corresponding to significant bits lower than the MSB-abit, applying the first reference voltage to first terminals of a first set of capacitors of the first capacitor array corresponding to significant bits higher than the MSB-abit, and applying the second reference voltage to first terminals of a second set of capacitors of the first capacitor array corresponding to the significant bits higher than the MSB-abit; subsequently, a weight of a capacitance of the capacitors corresponding to the MSB-abit is successively approximated.

Calibration system and method for SAR ADCs

A method of operating a redundant successive approximation analog-to-digital converter (ADC) includes: sampling an input signal; and successively approximating the sampled input signal using a digital-to-analog converter (DAC) including DAC reference elements having at least one sub-binary weighted DAC reference element. Successively approximating the sampled input signal includes performing a plurality of successive approximation cycles. Each successive approximation cycle of the plurality of successive approximation cycles including: generating a DAC input word using a successive approximation register (SAR), offsetting the DAC input word to form an offset DAC input word when the successive approximation cycle corresponds to the at least one sub-binary weighted reference element, applying the offset DAC input word to an input of the DAC to produce a first DAC output signal, comparing the first DAC output signal with the sampled input signal using a comparator, and setting a bit of the SAR based on the comparison.

System and method for a successive approximation analog-to-digital converter

A radio frequency digital-to-analog converter (RFDAC) circuit includes an RFDAC array circuit including an array of cells arranged into a plurality of segments. Each segment of the plurality of segments is configured to process input data signals. The RFDAC array circuit is configured to process an input data based on activating a set of segments of the plurality of segments, forming a set of active segments, and when the sign of the input data is changed, deactivate a partially active segment of the set of active segments and activate a sign change segment within the RFDAC array circuit. The sign change segment includes a segment within the plurality of segments of the RFDAC array circuit that is different from the set of active segments.

Signed-RFDAC architectures enabling wideband and efficient 5G transmitters

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Villach, Austria

Alan Paussa