Infineon Technologies Ag

Infienon Technologies Ag

Alan Morgan

Helmut Fischer

Peter Beer

A semiconductor device includes an integrated main circuit and an auxiliary circuit on a semiconductor substrate. The auxiliary circuit is configured to output and/or for receive electrical signals to and/or from the main circuit and is arranged at a distance from the main circuit in a kerf region of the semiconductor device. The main and auxiliary circuits each include a contact device that can be externally contact-connected to produce a temporary electrical signal connection between the main and auxiliary circuits.

Built off self test (BOST) in the kerf

A first and a second memory circuit are tested in parallel. It is possible to activate the memory circuits depending on a circuit select signal, and it is possible to apply a control signal to the first and second memory circuits. The control signal initiates a function in the respective memory circuit depending on the activation of the first or second memory circuit. In testing the memory circuits, the circuit select signal is applied to the first memory circuit and the inverted circuit select signal is applied to the second memory circuit, so that the function is initiated in the first or in the second memory circuit depending on the circuit select signal.

Test system and method for testing memory circuits

An addressing device selects an element from a set of N&lE;2 regular elements or alternatively from a set of R<N redundant elements in dependence on a K-bit input address which is applied to a 1-out-of-N decoder, and which addresses the regular elements. For each redundant element, a bypass circuit is provided and has in each case a reference bit transmitter for supplying K reference bits that are programmable by selective destruction or by selective introduction of conductive links in order to set a comparison device to the identification of a selected address. If the relevant address is identified, the bypass circuit addresses the redundant element assigned to it while switching off the 1-out-of-N decoder, provided that it is sensitized. For its sensitization, each bi-stable-circuit checks M<K preselected specimens of the reference bits in order to set the relevant bypass circuit into an active state if the binary values of these reference bits differ from a chosen bit combination.

Addressing device for selecting regular and redundant elements

Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Wafer with additional circuit parts in the kerf area for testing integrated circuits on the wafer

A semiconductor memory apparatus includes a first and second memory bank. Each of these memory banks has a plurality of row and column lines and at least one redundant column line. An activation device selectively activates the redundant column line, thereby causing the redundant column line to become a replacement line for a defective column line. The activation device includes a plurality of programmable addressing fuses, and a programmable selection fuse having at least two electrical selection fuse states. The programmable selection fuse is configured such that an addressing fuse in the first selection fuse state is electrically associated with the first memory bank and an addressing fuse in the second selection fuse state is electrically associated with the second memory bank.

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München, Germany

Alan Morgan