Silicon Laboratories Inc.

Motorola Corporation

Black Sand Technologies, Inc.

Alan Lee Westwick

Susanne A Paul

Axel Thomsen

Xiaoling Guo

Timothy Joseph Dupuis

Thomas Saroshan David

Dazhi Wei

Xiaodong Wang

John M Khoury

Jinwen Xiao

Clayton H Daigle

Pavel Konecny

Shahram Tadayon

Jia-Hau Liu

Bradley Martin

Roger A Whatley

Ricky Setiawan

Guillaume Crinon

Nicolas Constantinidis

Rex Wong Tak Ying

Alexandre Rouxel

Donelson Arthur Shannon

Gary Franzosa

Ka Yin Leung

Kenneth Wilson Fernald

Douglas S Piasecki

Douglas R Holberg

Kevin B Traylor

Marty Lynn Pflum

Sebastian Ahmed

Tamás Marozsák

Carlos A Greaves

Shouli Yan

Luis A Bonet

András Vince Horváth

Sean Anthony Lofthouse

Didier Gallais

Gabriel Vogel

Mauricio A Zavaleta

Michael Dale Floyd

David E Bush

Soh Kok Hong

James Alan Tuvell

Low Yung Lih

Todd L Barker

A gate driver with an integrated Miller clamp controls a high-power drive device coupled to a terminal of a package that houses an integrated circuit coupled to the terminal. A method includes generating an indication of a level of a signal on the terminal with respect to a predetermined signal level. The method includes configuring a variable strength driver of the integrated circuit to charge, discharge, or clamp the terminal based on a control signal and the indication.

Gate driver with integrated miller clamp

A switch controls current to be supplied to an inductive load when turned on. A clamp circuit clamps a flyback voltage resulting from turning off the switch. The clamp circuit has a first clamping voltage responsive to the switch being turned off, and has a second clamping voltage, higher than the first clamping voltage, responsive to a current level through the inductive load being lower than a predetermined current level. That ensures that as the current comes down to levels required to break contact, the clamp voltage is increased to speed the collapse of the magnetic field when needed to minimize contact wear by maintaining armature momentum.

Clamping inductive flyback voltage to reduce power dissipation

In some embodiments, a circuit may include a configurable logic module including a multiplexer. The multiplexer may include a plurality of data inputs configured to receive one or more bit strings. Each of the one or more bit strings may correspond to a logic operation. The multiplexer may further include a first control input configured to receive a first input signal, a second control input configured to receive a second input signal, and an output configured to provide an output signal corresponding to a selected logic operation based on the first input signal and the second input signal.

Configurable logic circuit including dynamic lookup table

A voltage regulator circuit with variable feedback is disclosed. In one embodiment, a voltage regulator includes an amplifier having a first input configured to receive a reference voltage and a second input configured to receive a feedback signal. The voltage regulator further includes first and second transistors each having respective gate terminals coupled to an output of the amplifier. A resistor network coupled to the second input of the amplifier and further coupled to the first and second transistors. The resistor network is configured to produce the feedback signal based on currents through the first and second transistors, respectively.

Voltage regulator with adjustable feedback

An apparatus includes an integrated circuit, which includes a processor and a driver. The integrated circuit is fabricated by a process that establishes a nominal maximum voltage for components of the integrated circuit. The driver is adapted to selectively electrically couple a voltage that is higher than the nominal maximum voltage to an external terminal of the integrated circuit.

Analog interface for a microprocessor-based device

Apparatus and associated methods are disclosed for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC to convert a digital input signal to an analog output signal. The DAC includes a decoder to decode the digital input signal and to provide first and second sets of control signals. The DAC also includes a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second set of control signals.

Apparatus for digital-to-analog conversion with improved performance and associated methods

An integrated circuit (IC) includes a plurality of pads adapted to send or receive signals, and a plurality of mixed signal interface blocks, each of which is coupled to a corresponding pad in the plurality of pads. Furthermore, each mixed signal interface block in the plurality of mixed signal interface blocks is adapted to be configurable to provide selected functionality independently of the other mixed signal interface blocks.

Apparatus for mixed signal interface circuitry and associated methods

Apparatus and associated methods are disclosed for gain programming or selection with parasitic element compensation. In one exemplary embodiment, an apparatus includes a first circuit that has a first programmable gain, and includes a first set of components having parasitic elements. The apparatus also includes a second circuit that has a second programmable gain, and includes a second set of components having parasitic elements. The apparatus has a gain that is a product of the first and second programmable gains. A gain error because of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as a reciprocal of the second programmable gain.

Apparatus for gain selection with compensation for parasitic elements and associated methods

Apparatus and associated methods are disclosed for gain and offset trimming. In one exemplary embodiment, an apparatus includes a first circuit that includes a first transconductance stage to generate a first current. The first circuit has an output offset. The apparatus further includes an offset trim circuit, which includes a second circuit to provide an output voltage selectable from a plurality of voltage values, and a second transconductance stage to generate a second current in response to the output voltage of the second circuit. The output offset of the first circuit is trimmed by adding the second current to the first current.

Apparatus for offset trimming and associated methods

An apparatus includes a microcontroller unit (MCU). The MCU includes a buffer and an analog comparator that are coupled to an input of the MCU. The MCU is adapted to selectively determine a logic value of a digital signal applied to the input of the MCU from an output signal of the buffer or from an output signal of the analog comparator.

Apparatus for improved signal communication in electronic circuitry and associated methods

An integrated circuit includes a shared synchronization bus having a plurality of channels assigned to one or more of a plurality of peripheral modules. The integrated circuit further includes a first peripheral module of the plurality of peripheral modules including a control output coupled to the shared synchronization bus and configured to communicate event timing data to an input of a second peripheral module of the plurality of peripheral modules through a selected one of the plurality of channels.

Integrated circuit, system, and method including a shared synchronization bus

A technique includes executing at least one instruction on a processor to control a driver circuit; and in response to a predetermined trigger condition, asynchronously causing the driver circuit to enter a predetermined state.

Technique and system to control a driver state

A system and method for generating an analog signal is disclosed. In one embodiment, system includes a first-in, first-out (FIFO) buffer configured to receive and store a plurality of digital values written to the FIFO buffer. The system further includes a digital-to-analog converter (DAC) coupled to read the digital values from the FIFO buffer and configured to convert the digital values to an analog signal. The FIFO buffer is configured to operate in a first mode in which writes to the FIFO buffer are inhibited and current digital values stored in the FIFO buffer are provided to the DAC in a repeating sequence.

Digital-to-analog converter resolution enhancement using circular buffer

Growing community of inventors

Austin, TX, United States of America

Alan Lee Westwick