Atmel Corporation

Alan L Renninger

Bohumil Lojek

James Shen

Volker Dudek

Johnny Chan

Philip S Ng

Michael Graf

Jinshu Son

Tsung-Ching Wu

Stefan Schwantes

Tin-Wai Wong

Jeffrey Ming-Hung Tsai

Gust Perlegos

Jeffrey M Tsai

Eleonore Daemen

James Yount

Maria Ryan

A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

Method and system for incorporating high voltage devices in an EEPROM

A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Circuit to control voltage ramp rate

A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold voltages. The lower threshold is selected to be at a zero charge state for one of the two logic levels of the memory.

SONOS memory array with improved read disturb characteristic

Disclosed is a self-aligned non-volatile memory cell including a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Self-aligned non-volatile memory cell

A method of fabricating a non-volatile memory embedded logic circuit having a low voltage logic gate oxide layer and tunnel oxide layer is described. Both the low voltage logic gate oxide and the tunnel oxide layers are formed in a single step, thereby reducing the number of overall processing steps needed to form the devices.

Method of forming a low voltage gate oxide layer and tunnel oxide layer in an EEPROM cell

Disclosed is a self-aligned non-volatile memory cell comprising a small sidewall spacer electrically coupled and being located next to a main floating gate region. Both the small sidewall spacer and the main floating gate region are formed on a substrate and both form the floating gate of the non-volatile memory cell. Both are isolated electrically from the substrate by an oxide layer which is thinner between the small sidewall spacer and the substrate; and is thicker between the main floating gate region and the substrate. The small sidewall spacer can be made small; therefore, the thin oxide layer area can also be made small to create a small pathway for electrons to tunnel into the floating gate.

Method of fabricating a self-aligned non-volatile memory cell

A tiny tunnel oxide window with dimensions smaller than the minimum feature resolution of the process equipment is formed in an EEPROM structure by placing dummy nitride spacers on either side of a nitride implant mask over a gate oxide layer after source and drain are formed by implantation at opposed sides of the nitride mask. The spacers are formed in a second nitride layer deposit after the nitride mask formation. The spacers are etched to have a desired tunnel oxide dimension. Another oxide layer is deposited over one of the source and drain regions, abutting a nitride spacer. The nitride layers are removed leaving a spacer nest, into which tunnel oxide is deposited. The device is finished in the usual way for an ESPROM structure.

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Cupertino, CA, United States of America

Alan L Renninger