Nvidia Corporation

Alan Kaatz

Jack H Choquette

Shirish C Gadre

Olivier Giroux

Manan Patel

Andrew Robert Kerr

Steven James Heinrich

Xiaogang Qiu

Omkar Paranjape

Poornachandra Rao

Ronny Krashinsky

Jeff Schottmiller

Sean Jeffrey Treichler

Alexander Lev Minkin

John Tran

Girish Bharambe

Kyrylo Perelygin

Harold Carter Edwards

Rishkul Kulkarni

Apoorv Parle

Maciej Piotr Tyrlik

Konstantinos Kyriakopoulos

Edward H Gornish

Aditya Avinash Atluri

Gokul Ramaswamy Hirisave Chandra Shekhara

Oliver Giroux

Balaji Krishna Yugandhar Atukuri

Bageshri Sathe

David Allan Berson

Haicheng Wu

Vijay Thakkar

Cody Addison

Aman Arora

James Player

Cris Cecka

A parallel processing unit comprises a plurality of processors each being coupled to a memory access hardware circuitry. Each memory access hardware circuitry is configured to receive, from the coupled processor, a memory access request specifying a coordinate of a multidimensional data structure, wherein the memory access hardware circuit is one of a plurality of memory access circuitry each coupled to a respective one of the processors; and, in response to the memory access request, translate the coordinate of the multidimensional data structure into plural memory addresses for the multidimensional data structure and using the plural memory addresses, asynchronously transfer at least a portion of the multidimensional data structure for processing by at least the coupled processor. The memory locations may be in the shared memory of the coupled processor and/or an external memory.

Method and apparatus for efficient access to multidimensional data structures and/or other large data blocks

Apparatuses, systems, and techniques to perform computational operations in response to one or more compute uniform device architecture (CUDA) programs. In at least one embodiment, one or more computational operations are to cause one or more other computational operations to wait until a portion of matrix multiply-accumulate (MMA) operations have been performed.

Application programming interface to wait on matrix multiply-accumulate

A technique for block data transfer is disclosed that reduces data transfer and memory access overheads and significantly reduces multiprocessor activity and energy consumption. Threads executing on a multiprocessor needing data stored in global memory can request and store the needed data in on-chip shared memory, which can be accessed by the threads multiple times. The data can be loaded from global memory and stored in shared memory using an instruction which directs the data into the shared memory without storing the data in registers and/or cache memory of the multiprocessor during the data transfer.

Techniques for efficiently transferring data to a processor

Growing community of inventors

Santa Clara, CA, United States of America

Alan Kaatz