Oak Technology, Inc.

Alan K Ng

Robert R Griffith

Roy M Wen

Ka Kit Ling

Don Smith

Neil H MacLean

A controller for use in an optical storage device is provided. The controller includes a block decoder/encoder for processing data to and from a media of the optical storage device. An ATAPI interface is also provided and is configured to process data and control signals for selectively communicating data to and from the optical storage device during operation in an ATAPI mode. Universal serial bus (USB) logic is configured to process data and control signals for selectively communicating data to and from the optical storage device during operation in a USB mode. The USB logic is configured to utilize data transfer control logic implemented by the ATAPI interface. Accordingly, the one controller can be integrated into either an external peripheral device that communicates over a USB connection in the USB mode, or into an internal peripheral device that communicates over an IDE connection in the ATAPI mode. The optical storage device can be any type of optical storage device, such as, for example a CD-RW, a CD-ROM, a CD-R, a DVD, and the like. Further, the optical storage device can be in the form of an internal or external peripheral device.

Controller for ATAPI mode operation and ATAPI driven universal serial bus mode operation and methods for making the same

An apparatus for automatically rendering both encoded and unencoded data files comprises a data processor and a decoder. The data processor receives a set of input data from a storage medium, such as an optical storage medium, and determines whether the set of input data is encoded or unencoded. If the input data is encoded, then the data processor provides to the decoder a set of encoded data, and generates an indication signal to cause the decoder to be activated. In response, the decoder decodes the set of encoded data and provides as output a set of decoded data. This decoded data may then be provided to a signal transport mechanism, such as a digital signal bus, to be rendered by a digital device such as a computer, or to a digital to analog converter which converts the decoded data into analog signals for driving an analog device, such as a speaker. On the other hand, if the data processor determines that the input data is unencoded, then the data processor processes the set of input data to derive a set of processed data, and provides this set of processed data at its output. No indication signal is generated; thus, the decoder is not activated. The processed data may then be provided to a signal transport mechanism, such as a digital signal bus, to be rendered by a digital device such as a computer, or to a digital to analog converter which converts the processed data into analog signals for driving an analog device, such as a speaker. Regardless of whether the input data is encoded or unencoded, the apparatus automatically renders it properly to a user.

Apparatus for automatically processing both encoded and unencoded data

A receiver interface for interfacing with an Advanced Technology Attachment Packet Interface (ATAPI) in a first device. The receiver interface includes a converter, a depacketizing circuit, and an ATAPI receiver circuit. The converter converts a first set of signals from a serial bus into a second set of signals. The first set of signals are serial to one another and use low-voltage, differential signaling (LVDS). The first set of signals are adapted to be received on fewer lines and at a faster data rate than possible with an Integrated Disc Electronics (IDE) bus. In contrast, the second set of signals are serial to another and use TTL voltage levels and single-ended signaling. Additionally, the second set of signals use a packet format to represent a packet. The depacketizing circuit disassembles the packet represented by the second set of signals to generate a third set of signals, which are parallel to one another and use TTL, single-ended signaling. The third set of signals represents a payload of the packet. The ATAPI receiver circuit stores a fourth set of signals at a location within the ATAPI in response to the third set of signals. The fourth set of signals representing a portion of the payload of the packet.

Apparatus and method for receiving data serially for use with an advanced technology attachment packet interface (atapi)

A transmission interface compatible with the AT Attachment Packet Interface (ATAPI) that achieves transfer rates greater than those possible with an Integrated Disc Electronics (IDE) bus. The transmission interface includes a transmission ATAPI circuit, a packetizing circuit and a converter. The transmission ATAPI circuit monitors the content of the ATAPI and, when a change is detected, generates a first set of signals representative of that change. The first set of signals are single-ended, parallel to one another and use Transistor-Transistor Logic (TTL) voltage levels. The packetizing circuit packetizes the first set of signals to generate a second set of signals, which representing a packet. The packet payload represents the change in the contents of the ATAPI. The second set of signals are also single-ended, parallel to one another and use TTL voltage levels. The converter converts the second set of signals into a third set of signals and couples these to a serial bus. The third set of signals are serial to one another, and use low voltage level, differential signaling. Thus, the third set of signal are suited for transmission by the serial bus, which includes many fewer wires than available in an IDE bus while operating at a faster data rate.

Apparatus and method for transmitting data serially for use with an advanced technology attachment packet interface (atapi)

An apparatus and method for interfacing integrated circuits having incompatible input-output signal offset voltages that is relatively inexpensive and yet is also insensitive to noise. The apparatus of the present invention includes a receiver circuit for receiving differential signals on a differential line, comprising: (1) an interface circuit coupled to the differential signal line for removing a first offset voltage from the differential signal and biasing the differential signal to generate a biased differential signal having a second offset voltage, the interface circuit including a plurality of capacitive devices, (2) a differential amplifier circuit coupled to the interface circuit for converting the biased differential signal into a single-ended signal, (3) a Schmitt trigger circuit coupled to the differential amplifier circuit for filtering the single-ended signal to generate a filtered single-ended signal and (4) a latch circuit coupled to the Schmitt trigger circuit for filtering and asynchronously latching the filtered single-ended signal to generate a sustained, filtered digital signal. The method of the present invention comprises the steps of: (1) capacitively removing a first offset voltage from the differential signal, (2) biasing the differential signal to generate a biased differential signal having a second offset voltage, (3) converting the biased differential signal into a single-ended signal, (4) filtering the single-ended signal using a hysteresis-loop transfer function to generate a filtered single-ended signal and (5) filtering and latching the filtered single-ended signal using a delayed regenerative feedback, hysteresis-loop transfer function to generate a sustained, filtered digital signal.

Growing community of inventors

Sunnyvale, CA, United States of America

Alan K Ng