Freescale Semiconductor,inc.

Nxp USA, Inc.

Alan Joseph Carlin

Hugo M Cavalcanti

Colin MacDonald

Chris C Dao

Donald L Tietjen

Robert N Ehrlich

George E Baker

Kenneth P Tumin

Hubert Glenn Carson, Jr

Jonathan W McCallum

Alex S Y Koh

A design verification system verifies an electronic device design based on a static model of the electronic device. The static model is an expression of the relationships between modules of the electronic device design and relationships between the behaviors of those modules that can be expressed as set of logical relationships. The static model does not rely on a time variable, but instead reflects a fixed set of relationships between the electronic device modules and between behaviors of the electronic device modules. The static model can be employed by a solver, that identifies whether or how the mathematical relationships of the static model can be reconciled, given a set of constraints. The solver results can be analyzed to identify whether there are errors in the device design, such as resource conflicts, failure of the design to achieve a desired configuration, and the like.

Static modelling of an electronic device

A device simulation system performs a set of tests by applying, for each test in the set, a corresponding test stimulus to a simulation of the electronic device. In response to each test stimulus, the simulation generates corresponding output information which the device simulation system compares to a specified expected outcome to identify a test result for that test stimulus. In addition, for each test stimulus, the device simulation system generates test coverage information indicating the particular configuration of the simulated electronic device that resulted from the stimulus. The device simulation system correlates the coverage information with the test results to identify correlation rules that indicate potential relationships between test results and configurations of the simulated device.

Correlation of test results and test coverage for an electronic device design

A design verification system automatically identifies coverage of different constraints for a static model of an electronic device. The static model can be employed by a tool, referred to as a solver, that identifies whether the mathematical relationships of the static model can be reconciled, given a set of user-defined constraints that indicate a desired configuration, or range of configurations, of the electronic device. After a solution for a particular set of user-defined constraints has been identified, a constraints adjustment module can identify, based on coverage information generated by the solver, if other sets of user-defined constraints were implicitly solved by the solver. If such other sets were implicitly solved, the adjustments module can mark the sets as solved, such that they will omitted from constraints used for subsequent solutions of the solver.

Monitoring coverage for static modelling of an electronic device

A device is configured with components to enable debugging of the device's entry into and exit from a low power mode. The device includes: core logic, debug components, and a power management module (PMM). When the device exits a low power mode in which the states of the debug components are lost, the PMM prevents the core logic from resuming processing operations until the debug components have been re-configured to their prior states. The PMM either holds the core logic in reset or alternatively withholds power to the core logic. Reconfiguration of the debug components is initiated by a connected debugger, which can set one or more control and status (CS) register values within the device. The CS register values determine when the PMM prevents the core logic processing from resuming and when the PMM enables core logic processing to resume following the device's return from low power mode.

Debugger recovery on exit from low power mode

An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Low pin count reset configuration

A method and system for transmitting binary-coded data use partitioning of data words in a plurality of data nibbles. The data nibbles are coded using modified a 1-bit hot coding format that transforms a data nibble in a data segment including a plurality of bit groups. A change in a digital state at a bit position in a more significant bit group is maintained at that bit position in less significant bit groups, and information is transmitted in a form of a transition between digital states. The data segments are transmitted in phases each including one bit group from each data segment. At a receiving terminal, the bit groups are converted back in the binary-coded data words. In one application, the invention is used to reduce power consumption during data transmissions to and from an integrated circuit device.

Method and system for transmitting data

A test pattern generation flow has a stimulus and a device under test (DUT) that operate together through a test bench. The test bench monitors and collects all the data necessary to generate a test program. This information is presented as a captured simulation that allows for ease of generating test software, as well as other simulations such as fault simulation and virtual test simulation. The complete and convenient information can be utilized to automate the development and/or easily manually develop and debug the test software.

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Austin, TX, United States of America

Alan Joseph Carlin