Arm Limited

Alan Jeremy Becker

Mudit Bhargava

Robert Campbell Aitken

Joel Thornton Irby

Chiloda Ashan Senerath Pathirane

Peter Logan Harrod

Mark Gerald LaVine

Loïc Pierron

Peter Vrabel

Chiloda Pathirane

An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.

Error recovery storage for non-associative memory

Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a direct access path between the memory built-in self-test circuitry and a memory entry which bypasses the memory error protection circuitry; the memory built-in self-test circuitry being configured to execute a test operation by writing a test value to a first memory entry of the memory circuitry having a first test memory address via the indirect access path; retrieving the test value and associated error protection code from the first memory entry by the direct access path; writing the retrieved test value and associated error protection code to a second memory entry having a second test memory address via the direct access path, there being a difference in at least one bit between the first test memory address and the second test memory address; and retrieving the test value and associated error protection code from the second memory entry via the indirect access path; the memory built-in self-test circuitry comprising fault detection circuitry configured to detect a fault condition when the result of the check operation performed by the memory error protection circuitry is inconsistent with the difference between the first test memory address and the second test memory address.

Apparatus and method

Disclosed are methods, systems and devices for operation of memory device. In one aspect, bit positions of a portion of a memory array may be placed in a first value state. Values to be written to the bit positions may be determined subsequent to placement of the bit positions in the first value state. Values at selected ones of the bit positions may then be changed from the first value state to a second value state while maintaining remaining unselected ones of the bit positions in the first value state so that the bit positions store or represent the values determined to be written to the bit positions.

Method, system and device for memory device operation

A data processing apparatus comprises at least one memory configured to store data; processing circuitry to access data in the at least one memory. Memory built-in self-test (MBIST) circuitry has an interface to access the at least one memory and is configured to perform a test procedure for testing at least one target memory location of the at least one memory. The test procedure involves at least writing test data to the target memory location. Diagnostic circuitry executes a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry. The MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory.

Data processing

A data processing apparatus includes a memory and memory protection circuitry for providing an operational path to the memory during operational use of the memory. A memory built-in self-test controllerperforms built-in self-test operations upon the memory using either an indirect test access path to the memory via the memory protection circuitry or a direct test access path to the memory which bypasses the memory protection circuitry. Thus, the correct operation of the memory protection circuitry itself can be tested in addition to the correct operation of the memory.

Memory protection circuitry testing and memory scrubbing using memory built-in self-test

A data processing apparatus has at least one memory and processing circuitry. A memory built-in self-test (MBIST) interface receives a MBIST request indicating that a test procedure is to be performed for testing at least one target memory location. Control circuitry detects the MBIST request and reserves for testing at least one reserved memory location including the target memory location. During the test procedure, the memory continues servicing memory transactions issued by the processing circuitry that target a memory location other than the reserved location reserved by the control circuitry. The processing circuitry is stalled if it attempts to access a reserved memory location. Testing consists of short bursts of transactions which occur infrequently. In this way, MBIST testing may continue while the processor is operation in the field with reduced performance impact.

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Bushey, United Kingdom

Alan Jeremy Becker