International Business Machines Corporation

Alan James Leslie

Gregory J Fredeman

Toshiaki Kirihata

John Matthew Safran

Darren Lane Anand

Subramanian Srikanteswara Iyer

Chandrasekharan Kothandaraman

Gregory John Uhlmann

William Paul Hovis

Phil Christopher Paone

Salvatore Nicholas Storino

David W Siljenberg

Wei Guo

A method for proactively preventing lithographic problems is disclosed, which employs information generated from layout patterns including hot spots in a first technology node to identify hot spots in a second technology node employing a scaled down minimum dimension. In this proactive approach, problematic patterns or complex product geometries are identified in a chip design layout of the second technology node based on detection, in the chip design layout, of topological features that are similar to topological features of known hot spots in the first technology node. The identified patterns are potential hot spots in the chip design layout for the second technology node. Known hot spots in layout patterns in the first technology node are topologically categorized to provide a database for performing the fault detection and diagnosis on the chip design layout.

Automated lithographic hot spot detection employing unsupervised topological image categorization

A one-time-programmable-read-only-memory (OTPROM) is implemented in a two-dimensional array of aggressively scaled suicide migratable e-fuses. Word line selection is performed by decoding logic operating at Vwhile the bit line drive is switched between Vand a higher voltage, V, for programming. The OTPROM is thus compatible with and can be integrated with other technologies without a cost adder and supports optimization of the high current path for minimal voltage drop during fuse programming. A differential sense amplifier with a programmable reference is used for improved sense margins and can support an entire bit line rather than sense amplifiers being provided for individual fuses.

Random access electrically programmable e-fuse ROM

A design structure embodied in a machine readable medium used in a design process includes an apparatus for sensing the state of a programmable resistive memory element device, the apparatus further including a latch device coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg, the latch device configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg; and the fuse and reference resistance legs further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

Design structure for improving sensing margin of electrically programmable fuses

A method for determining the state of a programmable resistive memory element includes passing a first level of current through a fuse leg and a reference resistance leg of a test circuit including the programmable resistive memory element; detecting a differential signal developed between a reference node and a fuse node of the test circuit as a result of the first level of current; passing a second level of current through the fuse leg and the reference leg of a test circuit, the second level of current being higher than the first level of current so as to enable detection of trip resistance of the test circuit at a lower value than with respect to the first level of current; and detecting a differential signal developed between the reference node and the fuse node of the test circuit as a result of the second level of current.

Method for improving sensing margin of electrically programmable fuses

An apparatus for sensing the state of a programmable resistive memory element device includes a latch device is coupled to a fuse node and a reference node, the fuse node included within a fuse leg and the reference node configured within a reference resistance leg. The latch device is configured to detect a differential signal developed between the reference node and the fuse node as the result of sense current passed through the fuse leg and the reference resistance leg. The fuse and reference resistance legs are further configured for first and second sensing modes, wherein the second sensing mode utilizes a different level of current than the first sensing mode.

Apparatus and method for improving sensing margin of electrically programmable fuses

A secure device for electronic voting employs a write-once vote-recording medium. The medium has an initial writing mode in which data can be written but not read and a subsequent reading mode whereby data can be read but writing is permanently disabled. Once switched from the writing mode to the reading mode, it cannot be switched back. A hardware mechanism provides successful write confirmation The medium can be installed like a cartridge into a vote-recording device. The voting device provides encryption/authorization that combines polling parameters with voter information to produce a 'fuse string'. For each vote, a fuse string is written to the array. The poll is 'closed' by switching the medium to &#x201c;read&#x201d; mode, preventing further modification or tampering. To read out the results of the poll, an auditor enters &#x201c;password&#x201d; information to decode/decrypt the recorded information.

Secure electronic voting device

An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

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Wappingers Falls, NY, United States of America

Alan James Leslie