Freescale Semiconductor,inc.

Nxp Usa, Inc.

Semiconductor Components Industries, LLC

Alan J Magnus

Justin Eugene Poarch

Weng Foong Yap

Jason R Wright

Stephen Ryan Hooper

Dwight Lee Daniels

Scott M Hayes

Douglas G Mitchell

Michael B Vincent

Zhiwei Gong

Colby Greg Rampley

Trung Duong

Jeffrey Lynn Weibrecht

Lianjun Liu

Darrell Glenn Hill

Chad S Dawson

Philip H Bowles

Vijay Sarihan

Lisa H Karlin

Eduard Jan Pabst

James J Wang

Fred Reece Clayton

Naresh C Saha

William C Stermer, Jr

Pamela A O'Brien

David Robert Currier

Elijah Blue Foster

Francisco Chaidez

Carl E D Acosta

Warren Crapse

A method of making a semiconductor device is provided for depositing, patterning, and developing photoresist () on an underlying layer located on a backside of a wafer having a frontside on which an integrated circuit die are formed over a shared wafer semiconductor substrate and arranged in a grid, thereby forming a patterned photoresist mask with a unique set of one or more openings which are used to selectively etch the underlying layer to form, on each integrated circuit die, a unique die mark identifier pattern of etched openings in the underlying layer corresponding to the unique set of one or more openings in the patterned photoresist mask (), where the patterned photoresist mask is removed () from the backside of the wafer before singulating the wafer to form a plurality of integrated circuit devices () which each include a unique die marking.

Using a backside mask layer for forming a unique die mark identifier pattern

A device wafer is provided that includes a substrate having major and minor surfaces, and a plurality of active devices located at the major surface. A eutectic alloy composition is formed at the minor surface of the substrate. The eutectic alloy composition is removed from the minor surface of the substrate such that a portion of the eutectic alloy composition remains at an outer perimeter of the minor surface to strengthen the outer perimeter of the substrate. A bonding layer is deposited over the minor surface and over the portion of the eutectic alloy composition at the outer perimeter of the minor surface. The bonding layer is utilized for joining semiconductor components of the device wafer to secondary structures. Additional eutectic alloy composition may remain on the minor surface of the substrate at the streets to strengthen the substrate during device wafer separation.

Method for increasing semiconductor device wafer strength

In making electronic component packages, a method includes forming a sacrificial material over a first temporary substrate, applying a second temporary substrate to the sacrificial material, and then curing the sacrificial material. After curing, the second temporary substrate is removed. The top surface of the sacrificial layer is defined by the second temporary substrate. After removal, a redistribution structure is formed on the top surface. After the formation of the redistribution structure, electronic components are applied to the redistribution structure. The electronic components are encapsulated to form an encapsulated panel. The first temporary substrate and the sacrificial material are removed. The panel is singulated into multiple electronic component packages.

Method for making an electronic component package

An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active surface including bond pads and a package body encapsulating the electronic component. The package body includes a principle surface coplanar with the active surface, A localized redistribution layer (RDL) dielectric layer is on the active surface. A localized RDL conductive layer is on the localized RDL dielectric layer and is coupled to the bond pads through openings in localized RDL dielectric layer. A primary RDL dielectric layer encloses the entire embedded component substrate and directly contacts the localized RDL dielectric layer, the localized RDL conductive layer, and the principal surface of the package body. The localized RDL conductive layer provides additional space for routing of additional interconnects while the localized RDL dielectric layer acts as a stress buffer.

Localized redistribution layer structure for embedded component package and method

Microelectronic packages and methods for fabricating microelectronic packages having optical mask layers are provided. In one embodiment, the method includes building redistribution layers over the frontside of a semiconductor die. The redistribution layers includes a body of dielectric material in which a plurality of interconnect lines are formed. An optical mask layer is formed over the frontside of the semiconductor die and at least a portion of the redistribution layers. The optical mask layer has an opacity greater than the opacity of the body of dielectric material and blocks or obscures visual observation of an interior portion of the microelectronic package through the redistribution layers.

Optically-masked microelectronic packages and methods for the fabrication thereof

An embedded component package includes an embedded component substrate. The embedded component substrate includes an electronic component having an active surface including bond pads and a package body encapsulating the electronic component. The package body includes a principle surface coplanar with the active surface. A localized redistribution layer (RDL) dielectric layer is on the active surface. A localized RDL conductive layer is on the localized RDL dielectric layer and is coupled to the bond pads through openings in localized RDL dielectric layer. A primary RDL dielectric layer encloses the entire embedded component substrate and directly contacts the localized RDL dielectric layer, the localized RDL conductive layer, and the principal surface of the package body. The localized RDL conductive layer provides additional space for routing of additional interconnects while the localized RDL dielectric layer acts as a stress buffer.

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers are provided. In one embodiment, the method includes building inner redistribution layers over a semiconductor die. Inner redistribution layers include a body of dielectric material containing metal routing features. A routing-free dielectric block is formed in the body of dielectric material and is uninterrupted by the metal routing features. An outer redistribution layer is produced over the inner redistribution layers and contains a metal plane, which is patterned to include one or more outgassing openings overlying the routing-free dielectric block. The routing-free dielectric block has a minimum width, length, and depth each at least twice the thickness of the outer redistribution layer.

Wafer level packages and methods for producing wafer level packages having delamination-resistant redistribution layers

A method includes applying a compressive force against MEMS structures at a front side of a MEMS wafer using a protective material covering at least a portion of the front side of the MEMS wafer. The method further includes concurrently dicing through the protective material and the MEMS wafer from the front side to produce a plurality of MEMS dies, each of which includes at least one of the MEMS structures. The protective material is secured over the front side of the MEMS wafer to apply pressure to the protective material, and thereby impart the compressive force against the MEMS structures to largely limit movement of the MEMS structures during dicing. A tack-free surface of the protective material enables its removal following dicing.

Method for shielding MEMS structures during front side wafer dicing

A structure to improve saw singulation quality and wettability of integrated circuit packages () is assembled with lead frames () having half-etched recesses () in leads. In one embodiment, the structure is a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the lead frame strip. In another embodiment, the structure is a semiconductor device package () that includes a semiconductor device encapsulated in a package body () having a plurality of leads (). Each lead has an exposed portion external to the package. There is recess () at a corner of each lead. Each recess has a generally concave configuration. Each recess is filled with a removable material ().

Semiconductor device package and method of manufacture

An embodiment of an electronic device includes an IC die with a top surface and a bond pad exposed at the top surface. A stud bump (or stack of stud bumps) is connected to the bond pad, and the stud bump and die are encapsulated with encapsulant. A trench is formed from a top surface of the encapsulant to the stud bump, resulting in the formation of a trench-oriented surface of the stud bump, which is exposed at the bottom of the trench. An end of an interconnect is connected to the trench-oriented surface of the stud bump. The interconnect extends above the encapsulant top surface, and may be coupled to another IC die of the same electronic device, another IC die that is distinct from the device, or another conductive feature of the device or a larger electronic system in which the device is incorporated.

Electronic devices with embedded die interconnect structures, and methods of manufacture thereof

Wafer level packages and methods for producing wafer level packages having non-wettable solder collars are provided. In one embodiment, the method includes forming solder mask openings in a solder mask layer exposing regions of a patterned metal level underlying the solder mask layer. Before or after forming solder mask openings in the solder mask layer, non-wettable solder collars are produced extending partially over the exposed regions of the patterned metal level. Solder balls are deposited onto the non-wettable solder collars and into the solder mask openings such that circumferential clearances are provided around base portions of the solder balls and sidewalls of the solder mask layer defining the solder mask openings.

Wafer level packages having non-wettable solder collars and methods for the fabrication thereof

A MEMS wafer () includes a front side () having a plurality of MEMS structure sites () at which MEMS structures () are located. A method () for protecting the MEMS structures () includes applying () a non-active feature () on the front side of the MEMS wafer in a region that is devoid of the MEMS structures and mounting () the front side of the MEMS wafer in a dicing frame () such that a back side () of the MEMS wafer is exposed. The MEMS wafer is then diced () from the back side into a plurality of MEMS dies ().

Shielding MEMS structures during wafer dicing

Microelectronic packages having layered interconnect structures are provided, as are methods for the fabrication thereof. In one embodiment, the method includes forming a first plurality of interconnect lines in ohmic contact with a first bond pad row provided on a semiconductor. A dielectric layer is deposited over the first plurality of interconnect lines, the first bond pad row, and a second bond pad row adjacent the first bond pad row. A trench via is then formed in the dielectric layer to expose at least the second bond pad row therethrough. A second plurality of interconnect lines is formed in ohmic contact with the second bond pad row within the trench via. The second plurality of interconnect lines extends over the first bond pad row and is electrically isolated therefrom by the dielectric layer to produce at least a portion of the layered interconnect structure.

Microelectronic packages having layered interconnect structures and methods for the manufacture thereof

Microelectronic packages and methods for fabricating microelectronic packages having texturized solder pads, which can improve solder joint reliability, are provided. In one embodiment, the method includes forming a texturized dielectric region having a texture pattern, such as a hatch pattern, in an under-pad dielectric layer. A texturized solder pad is produced over the texturized dielectric region. The texturized solder pad has a solder contact surface to which the texture pattern is transferred such that the area of the solder contact surface is increased relative to a non-texturized solder pad of equivalent dimensions.

Microelectronic packages having texturized solder pads and methods for the fabrication thereof

A structure and method to improve saw singulation quality and wettability of integrated circuit packages () assembled with lead frames () having half-etched recesses () in leads. A method of manufacturing lead frames includes providing a lead frame strip () having a plurality of lead frames. Each of the lead frames includes a depression () that is at least partially filled with a material () prior to singulating the lead frame strip.

Growing community of inventors

Gilbert, AZ, United States of America

Alan J Magnus