Gainspan Corporation

Loral/rohm Mil-Spec Corp.

Alan J Herring

Pankaj Vyas

Dipankar Talukdar

Gregory Winner

John A Hiller

Richard J Tobias

Craig R Morgan

Jon K Elliott

Lewis E Adams, Iii

Peter D Hunt

A system includes a device and a wireless network. The device uses multiple wireless communication protocols. The wireless network is coupled to the device by the multiple wireless communication protocols. The device simultaneously uses two of more of the multiple wireless communication protocols. The wireless communication protocols and the wireless communication export protocols include WiFi, ZigBee and Bluetooth.

Concurrent mode radio

A cache system includes a processor chip to receive a processing unit address. The cache system also includes a comparator to compare the processing unit address to an address information stored in an allocated tag subset of a tag memory of the processor chip to determine whether the processing unit address matches the address information. The cache system further includes a mapping device to map the portion of the address information to an external memory data, temporarily stored in an allocated data memory subset and a corresponding data memory set of a data memory in the processor. Furthermore, the cache system includes a stacking loop to prioritize the allocated tag subset and a corresponding tag set when the processing unit address matches the address information.

External memory tagging and stack ordering of memory tags

A method is employed for pre-assignment and pre-scheduling of tasks that enables allocation across multiple physical processors arranged in a variety of architectures. The method comprises the steps of: constructing a DFG of tasks to be performed to provide a solution for a problem; determining cost values for each task and the overall problem, such cost values taking into account a target multiprocessor architecture and factors such as elapsed task execution times. The method pre-assigns the tasks to logical processors and assures that inter-dependent tasks are executable by logical processors that are within required communications delay criteria of each other. The assigning action attempts to arrive at a minimal cost value for all tasks comprising the problem. The pre-assigned tasks are then pre-scheduled based upon a performance criteria and are converted to machine code. The machine code is then deployed to physical processors in the target multi-processor architecture. The deploying action maps the logical processors' pre-assigned programs (comprising assigned tasks) onto physical processors, using data regarding the multi-processor architecture and the current utilization of the physical processors in the architecture, all while assuring that inter-dependent tasks are mapped so as to fulfill interprocessor communication delay criteria.

Method for automated deployment of a software program onto a

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San Jose, CA, United States of America

Alan J Herring