International Business Machines Corporation

Alan Grant Singletary

Robert Christopher Dixon

Akash V Giri

Darin Marcus Greene

Barry Joe Wolford

Abraham Arevalo

Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses

Exemplary methods, apparatuses, and products are described for creating a behavioral model of a hardware device for use in a simulation environment. The behavioral model is created by an iterative process that includes receiving in a simulated hardware device from a simulated device under test ('DUT') a stimulus waveform. The stimulus waveform includes data representing a number of stimuli. In response to receiving the stimulus waveform, the simulated hardware device presents a recorded response waveform from a recorded response file to the DUT. The stimulus waveform is also recorded. The recorded stimulus waveform is presented to the hardware device. A response waveform that results from presenting the recorded stimulus waveform to the hardware device is recorded in the recorded response file.

Creating a behavioral model of a hardware device for use in a simulation environment

In one aspect, a method for performing clocked operations in a device includes performing, in a device, first and second operations responsive to a clock having a primary frequency f. The device is capable of performing the operations within X and Y cycles of the clock, respectively. X cycles of the clock correspond to a time interval Twith the clock operating at the frequency f, and, accordingly, the device is capable of performing X/Y instances of the second operation within time interval Twith the clock operating at the frequency f. During the time interval Tat least one extra cycle of the clock is generated to reduce performance time for the first operation. An affect of the at least one extra cycle is masked with respect to the second operation, so that instances of the second operation during the interval Tremain no greater in number than X/Y.

Method, apparatus, and computer program product for pacing clocked operations

In one aspect of the invention, a method for testing includes interposing a tester between first and second logic. The first logic and second logic have respective first and second output drivers. The tester operates in test cycles to detect dynamic contention responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during an immediately succeeding one of the test cycles. Static contention is detected responsive to a signal asserted by the first driver during one of the test cycles and a signal asserted by the second driver during the same one of the test cycles.

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Austin, TX, United States of America

Alan Grant Singletary