Texas Instruments Corporation

Future Wei Technologies, Inc.

Other

Alan Gatherer

Anand Ganesh Dabak

Timothy M Schmidl

Hao Luan

Sushma Wokhlu

Srinath Hosur

Ashish Rai Shrivastava

Alan V McCree

Michael Oliver Polley

Vishu R Viswanathan

Lee Dobson McFearin

Stephen J Perkins

Alex Elisa Chandra

Keith L Quiring

Peter Yan

Tod David Wolf

Mohammed Nafie

Debashis Bhattacharya

Mark W Brown

Eko Nugroho Onggosanusi

Fang Yu

Murtaza Ali

Krishnasamy Anandakumar

Sriram Vishwanath

Hardik Jain

Everest Huang

Casen Hunger

Tarik Muharemovic

Sundararajan Sriram

Donald Phillip Shaver

Dale E Hocevar

Carl E Lemonds, Jr

Krishanasamy Anandakumar

Aris Papasakellariou

Shivaling S Mahant-Shetti

Bin Yang

Ching-Yu Hung

Tong Sun

Dennis G Mannering

Ywhpyng Harn

Xiaotao Chen

Ray A King

Xingfeng Chen

Yan Bei

Xiaolin Lu

Anthony C K Soong

Wei Zhu Chen

Gene A Frantz

Hiep V Tran

Arthur John Redfern

Carl Michael Panasik

John William Fattaruso

Song Wu

Walter Y Chen

John Charles Linn

Domingo G Garcia

Michael L McMahan

Yang Zhou

Douglas B Weiner

Carl E Lemonds

Zhuolei Wang

Vijay Sundararajan

Antonio F Mondragon-Torres

Adam M Chellali

William C Timm

Terence J Riley

Shigenori Kinjo

Jun Ying

Paul E Schurr

Sriram Sundararajan

Chushun Huang

Mehran Bagheri

Xi Chen

Yichuan Yu

Jinseok Choi

Armelle Laine

Xiaodong Wang

Ke Ning

Rong Chen

Technology for providing data to a processing unit is disclosed. A computer processor may be divided into a master processing unit and consumer processing units. The master processing unit at least partially decodes a machine instruction and determines whether data is needed to execute the machine instruction. The master processing unit sends a request to memory for the data. The request may indicate that the data is to be sent from the memory to a consumer processing unit. The data sent by the memory in response to the request may be stored in local read storage that is close to the consumer processing unit for fast access. The master processing unit may also provide the machine instruction to the consumer processing unit. The consumer processing unit may access the data from the local read storage and execute the machine instruction based on the accessed data.

Main processor prefetching operands for coprocessor operations

It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

System and method for shared memory ownership using context

A system and method for variable lane architecture includes memory blocks located in a memory bank, one or more computing nodes forming a vector instruction pipeline for executing a task, each of the computing nodes located in the memory bank, each of the computing nodes executing a portion of the task independently of other ones of the computing nodes, and a global program controller unit (GPCU) forming a scalar instruction pipeline for executing the task, the GPCU configured to schedule instructions for the task at one or more of the computing nodes, the GPCU further configured to dispatch an address for the memory blocks used by each of the computing nodes to the computing nodes.

System and method for variable lane architecture

A data warehouse engine (DWE) includes a central processing unit (CPU) core and a first data organization unit (DOU), where the first DOU is configured to aggregate read operations. The DWE also includes a first command queue coupled between the CPU core and the first DOU, where the first command queue is configured to convey commands from the CPU core to the first DOU.

System and method for data warehouse engine

A computation system-on-a-chip (CSoC) includes a first scalable distributed real-time Data Warehousing (sdrDW) engine and a network interface coupled to the first sdrDW engine, where the network interface is coupled to an interconnect, and where the CSoC is configured to transmit a task request over the interconnect to a first networked bulk storage controller (NBSC) requesting that a task be performed on a bulk storage medium.

System and method for scalable distributed real-time data warehouse

A distributed and shared memory controller (DSMC) comprises at least one building block. comprising a plurality of switches distributed into a plurality of stages; a plurality of master ports coupled to a first stage of the switches; and a plurality of bank controllers with associated memory banks coupled to a last stage of the switches; wherein each of the switches connects to lower stage switches via internal connections, each of the switches of the first stage connects to at least one of the master ports via master connections and each of the switches of the last stage connects to at least one of the bank controllers via memory connections; wherein each of the switches of the first stage connects to second stage switches of a neighboring building block via outward connections and each of the switches of a second stage connects to first stage switches of the neighboring building block via inward connections.

Distributed and shared memory controller

A method includes determining an error vector magnitude for analog signals received by multiple antennas in an array of antennas of a base station, assigning quantization bits to a plurality of analog-to-digital converters (ADCs) of the base station such that some ADCs have different numbers of quantization bits allocated from a fixed total number of available quantization bits of the base station, and applying the analog signals to the ADCs with quantization bits assigned to reduce the error vector magnitude of the analog signals.

ADC bit allocation under bit constrained MU-massive MIMO systems

A method includes receiving, by a real-time Data Warehouse (rDW) from a first task, a first dataset and spreading the first dataset to produce a first plurality of objects, where the first plurality of objects includes a first object and a second object. The method also includes storing the first object in a first location in an rDW data repository and storing the second object in a second location in the rDW data repository.

System and method for real-time data warehouse

A method, system, and architecture for efficiently accessing data in a memory shared by multiple processor cores that reduces the probability of bank conflicts and decreases latency is provided. In an embodiment, a method for accessing data in a memory includes determining, by a scheduler, a read pattern for reading data from memory to serve requests in a plurality of bank queues, the memory comprising a plurality of memory banks and a plurality of coding banks, the coding banks storing a coded version of at least some of the data stored in the plurality of memory banks; reading a first data from a first memory bank; reading coded data from one of the coding banks; and determining the second data according to the coded data and the first data.

Intelligent coded memory architecture with enhanced access scheduler

A data streaming unit (DSU) and a method for operating a DSU are disclosed. In an embodiment the DSU includes a memory interface configured to be connected to a storage unit, a compute engine interface configured to be connected to a compute engine (CE) and an address generator configured to manage address data representing address locations in the storage unit. The data streaming unit further includes a data organization unit configured to access data in the storage unit and to reorganize the data to be forwarded to the compute engine, wherein the memory interface is communicatively connected to the address generator and the data organization unit, wherein the address generator is communicatively connected to the data organization unit, and wherein the data organization unit is communicatively connected to the compute engine interface.

Data streaming unit and method for operating the data streaming unit

Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m&#x2212;k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

NoC interconnect with linearly-tunable QoS guarantees for real-time isolation

The present disclosure relates to a system and method of managing operation of a cache memory. The system and method assign each nested task a level, and each task within a nested level an instance. Using the assigned task levels and instances, the cache management module is able to determine which cache entries to evict from cache when space is needed, and which evicted cache entries to recover upon completion of preempting tasks.

Caching structure for nested preemption

A controller for a shared memory is disclosed. The controller comprises a transaction scanner configured to scan-in a plurality of transactions to access the shared memory and to divide the transactions into beat-level memory access commands. The controller also comprises a command super-arbiter comprising a plurality of command arbiters corresponding to a plurality of shared memory blocks in the shared memory. The command super-arbiter is configured to access a quality of service for each of the transactions, arbitrate the beat-level memory access commands associated with the transactions based on the quality of service for each of the plurality of transactions, and dispatch the beat-level memory access commands to the shared memory blocks based on results of arbitrating the beat-level memory access commands.

Shared memory controller and method of using same

Growing community of inventors

Richardson, TX, United States of America

Alan Gatherer