Micron Technology Incorporated

Aptina Imaging Corporation

Other

Round Rock Research, LLC

Micron Semiconductor, Inc.

Micron Technoloy, Inc

Alan G Wood

Warren M Farnworth

Salman Akram

David R Hembree

James M Wark

Kyle K Kirby

William Mark Hiatt

John O Jacobson

Tim J Corbett

Trung Tri Doan

Charles Martin Watkins

Derek J Gochnour

Sidney B Rigg

Mike Brooks

Michael E Hess

Peter A Benson

Larry Duane Kinsman

Eugene H Cloud

Tongbi T Jiang

Kevin G Duesman

Rich Fogal

Steven David Oliver

Robert J Folaron

Lelan D Warren

Jay C Nelson

Jennifer L Folaron

Pete A Benson

Mark E Tuttle

Syed Sajid Ahmad

C Patrick Doherty

Andrew J Krivy

Lu Velicky

Ford B Grigg

J Michael Brooks

Gary L Chadwick

Chender Huang

Dean A Klein

Philip J Ireland

J Mike Brooks

Rickie C Lake

Steve Oliver

Ed A Schrock

Mark Hiatt

Jason L Fuller

Mike Hess

George P McGill

Douglas M Kelly

Timothy J Allen

Larry D Cromar

Warren M Earnworth

Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect.

Semiconductor constructions

Semiconductor constructions having through-substrate interconnects

A semiconductor module system includes a module substrate and a semiconductor substrate having a through wire interconnect bonded to an electrode on the module substrate. The through wire interconnect includes a via, a wire in the via having a first end bonded to a substrate contact on the semiconductor substrate and a polymer layer at least partially encapsulating the wire. The semiconductor module system can also include a second substrate stacked on the semiconductor substrate having a second through wire interconnect in electrical contact with the through wire interconnect.

Semiconductor module system having encapsulated through wire interconnect (TWI)

A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from the first side to the second side thereof; a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate; a dielectric material in the via configured to electrically insulate the wire from the semiconductor substrate; a bonding member bonded to the first end of the wire and to the substrate contact configured to secure the wire to the substrate contact; and a contact on the second end of the wire.

Through wire interconnect (TWI) for semiconductor components having wire in via and bonded connection with substrate contact

Methods of forming through-substrate interconnects

Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.

Method of forming vias in semiconductor substrates and resulting structures

A method for fabricating a through wire interconnect for a semiconductor substrate having a substrate contact includes the steps of: forming a via through the semiconductor substrate from a first side to a second side thereof; placing a wire in the via having a first end with a bonded connection to the substrate contact and a second end proximate to the second side; forming a first contact on the wire proximate to the first side; forming a second contact on the second end of the wire; and forming a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed.

Method for fabricating a through wire interconnect (TWI) on a semiconductor substrate having a bonded connection and an encapsulating polymer layer

A method for fabricating semiconductor components includes the steps of providing a semiconductor substrate having a circuit side, a back side and integrated circuits and circuitry on the circuit side; thinning the substrate from the back side to a selected thickness to form a thinned substrate; applying a dopant to the back side of the thinned substrate; and laser processing the back side of the thinned substrate to form a plurality of patterns of lasered features containing the dopant. The dopant can be selected to modify properties of the semiconductor substrate such as carrier properties, gettering properties, mechanical properties or visual properties.

Method for fabricating semiconductor components having lasered features containing dopants

Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods are disclosed herein. A method for packaging microfeature devices in accordance with an embodiment of the invention can include releasably attaching a plurality of first known good microelectronic dies to a carrier substrate in a desired arrangement. In several embodiments, for example, the first dies can be releasably attached to an attachment feature on the carrier substrate. The method can also include attaching one or more second known good microelectronic dies to the individual first dies in a stacked configuration to form a plurality of stacked devices. The method further includes at least partially encapsulating the stacked devices and separating the stacked devices from each other.

Methods for wafer-level packaging of microfeature devices and microfeature devices formed using such methods

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Through-wafer interconnects for photoimager and memory wafers

A through wire interconnect for a semiconductor substrate includes a via extending through the semiconductor substrate from a first side to a second side thereof, and a wire in the via electrically insulated from the semiconductor substrate having a first end with a bonded connection to the substrate contact and a second end proximate to the second side of the semiconductor substrate. The through wire interconnect also includes a first contact on the wire proximate to the first side of the semiconductor substrate, a second contact on the second end of the wire, and a polymer layer on the first side at least partially encapsulating the wire while leaving the first contact exposed. The through wire interconnect can also include a bonding member bonded to the first end of the wire and to the substrate contact having a tip portion forming the first contact.

Through wire interconnect (TWI) having bonded connection and encapsulating polymer layer

A stacked semiconductor component includes a semiconductor substrate having a substrate contact, a substrate opening extending to an inner surface of the substrate contact, and a conductive interconnect comprising a wire in the substrate opening having a wire bonded connection with the inner surface of the substrate contact. The stacked semiconductor component also includes a second substrate stacked on the semiconductor substrate having a contact bonded to the conductive interconnect on the semiconductor substrate. The second substrate can also include conductive interconnects in the form of wire bonded wires, and the stacked semiconductor substrate can include a third semiconductor substrate stacked on the second substrate.

Stacked semiconductor components having conductive interconnects

A semiconductor component includes a thinned semiconductor substrate having a back side and a circuit side containing integrated circuits and associated circuitry. The semiconductor component also includes at least one lasered feature on the back side configured to provide selected electrical or physical characteristics for the substrate. The lasered feature can cover the entire back side or only selected areas of the back side, and can be configured to change electrical properties, mechanical properties or gettering properties of the substrate.

Thinned semiconductor components having lasered features and method of fabrication

A semiconductor component includes a semiconductor substrate having a substrate contact, and a through wire interconnect (TWI) bonded to the substrate contact. The through wire interconnect (TWI) includes a via through the substrate contact and the substrate, a compressed wire in the via bonded to the substrate contact, and a contact on the wire. A stacked semiconductor component includes the semiconductor substrate, and a second semiconductor substrate stacked on the substrate and bonded to a through wire interconnect on the substrate.

Stacked semiconductor component having through wire interconnect (TWI) with compressed wire

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Boise, ID, United States of America

Alan G Wood