International Business Machines Corporation

Intel Corporation

Globalfoundries Inc.

Alan G Gara

Dong Chen

Philip Heidelberger

Martin Ohmacht

Mark Edwin Giampapa

Matthias Augustin Blumrich

Valentina Salapura

Paul William Coteus

Pavlos Michael Vranas

Todd Edward Takken

Dirk Hoenicke

Burkhard D Steinmacher-Burow

Burkhard Steinmacher-Burow

Gerard Vincent Kopcsay

Michael K Gschwind

Krishnan Sugavanam

Thomas M Gooding

Dong Chen Chen

George L Chiu

Rudolf Adriaan Haring

David L Satterfield

Robert E Walkup

Alexandre E Eichenberger

Robert Matthew Senger

Noel A Eisley

Yutaka Sugawara

Peter Boyle

Norman Christ

Robert William Wisniewski

Thomas Mario Cipolla

Gyan Vatsaraja Bhanot

Thomas A Liebsch

Ralph E Bellofatto

Chen-Yong Cher

James Anthony Marcella

Matthew Roger Ellavsky

Don Darrell Reed

Luis H Ceze

Lawrence Shungwei Mok

Kathryn Mary O'Brien

Mark Gregory Megerian

Shawn Anthony Hall

Barry Marshall Trager

Todd Alan Inglett

Kristan D Davis

Kahn C Evans

John Edward Sheets, Ii

Pradip Bose

Michael A Blocksome

Eren Kursun

Joseph D Ratterman

Adam James Muff

David Paul Paulsen

Vijayalakshmi Srinivasan

Hans Mikael Jacobson

Bruce Martin Fleischer

John A Gunnels

Sameh W Asaad

Thomas Winters Fox

John Kevin O'Brien

Mark James Jeanson

Peng Wu

Shurong Tian

Charles David Wait

Thomas R Puzak

Sameer Kumar

Jon K Kriegel

Wayne Melvin Barrett

Jeffrey John Parker

Craig Brian Stunkel

Douglas R Miller

Amith R Mamidala

Xiaotong Zhuang

Jose R Brunheroto

Michael B Mundy

Brian Andrew Schuelke

Richard A Swetz

Changhoan Kim

James Lee Van Oosten

Samuel J Miller

Gabor J Dozsa

Ruth Janine Poole

Brant L Knudson

Rory D Jackson

Brian E Smith

Simon C Steely, Jr

Devadatta V Bodas

John H Crawford

Kent D Glossop

Jonathan M Eastep

William Thomas Flynn

Kermin Elliott Fleming, Jr

Shmuel Winograd

Gheorghe Almasi

Paul Gregory Crumley

James C Sexton

Ramkumar Nagappan

Thomas Edward Musta

Lance G Hehenberger

Brandon Edward Schenck

Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.

Embedding global barrier and collective in a torus network

Methods, systems and computer program products are disclosed for measuring a performance of a program running on a processing unit of a processing system. In one embodiment, the method comprises informing a logic unit of each instruction in the program that is executed by the processing unit, assigning a weight to each instruction, assigning the instructions to a plurality of groups, and analyzing the plurality of groups to measure one or more metrics. In one embodiment, each instruction includes an operating code portion, and the assigning includes assigning the instructions to the groups based on the operating code portions of the instructions. In an embodiment, each type of instruction is assigned to a respective one of the plurality of groups. These groups may be combined into a plurality of sets of the groups.

Opcode counting for performance measurement

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements is to perform a second operation when an incoming operand set arrives at the plurality of processing elements.

Processors, methods, and systems with a configurable spatial accelerator

A method and system are disclosed for providing combined error code protection and subgroup parity protection for a given group of n bits. The method comprises the steps of identifying a number, m, of redundant bits for said error protection; and constructing a matrix P, wherein multiplying said given group of n bits with P produces m redundant error correction code (ECC) protection bits, and two columns of P provide parity protection for subgroups of said given group of n bits. In the preferred embodiment of the invention, the matrix P is constructed by generating permutations of m bit wide vectors with three or more, but an odd number of, elements with value one and the other elements with value zero; and assigning said vectors to rows of the matrix P.

Combined group ECC protection and subgroup parity protection

A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Collective network for computer structures

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

Apparatus and methods may provide for characterizing a plurality of similar components of a distributed computing system based on a maximum safe operation level associated with each component and storing characterization data in a database and allocating non-uniform power to each similar component based at least in part on the characterization data in the database to substantially equalize performance of the components.

Mitigating component performance variation

A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.

Managing power consumption and performance of computing systems

In a multiprocessor system, a conflict checking mechanism is implemented in the L2 cache memory. Different versions of speculative writes are maintained in different ways of the cache. A record of speculative writes is maintained in the cache directory. Conflict checking occurs as part of directory lookup. Speculative versions that do not conflict are aggregated into an aggregated version in a different way of the cache. Speculative memory access requests do not go to main memory.

Cache as point of coherence in multiprocessor system

A multiprocessor system supports multiple concurrent modes of speculative execution. Speculation identification numbers (IDs) are allocated to speculative threads from a pool of available numbers. The pool is divided into domains, with each domain being assigned to a mode of speculation. Modes of speculation include TM, TLS, and rollback. Allocation of the IDs is carried out with respect to a central state table and using hardware pointers. The IDs are used for writing different versions of speculative results in different ways of a set in a cache memory.

Multiprocessor system with multiple concurrent modes of execution

A method of testing a circuit includes halting a flow of normal data through the circuit, running test data through the circuit while subjecting the circuit to a stress condition, and determining whether a hard error exists in the circuit based on the running of the test data.

Dynamic hard error detection

Embedding global and collective in a torus network with message class map based tree path selection

An apparatus for detecting hard errors in a circuit includes a storage device and a processing circuit. The storage has stored therein test data and normal data. The processing circuit includes combinational logic in series with at least one set of input latches and at least one set of output latches. The apparatus includes a test control module configured to control the processing circuit to halt a flow of normal data through the processing circuit and run the test data through the processing circuit while subjecting the processing circuit to a stress condition.

Growing community of inventors

Nount Kisco, NY, United States of America

Alan G Gara