Microsoft Technology Licensing, LLC

Slt Logic, LLC

Intel Corporation

Slt Logics, LLC

Alan Fiedler

Georgios Asmanis

Matthew E Becker

Todd A Hinck

Jose Robins

A clock monitor circuit detects departures from expected values for clock period, clock high time duration, or clock low time duration. A delay line of the clock monitor circuit is composed of delay portions of delay cells. Each delay cell also has a comparator portion with logic to compare aspects of the monitored clock signal to corresponding expected values, and to output a failure detection signal indicating whether the expected values are met. Expected values may be read from a fuse set. The delay of the delay line may be programmatically adjusted. The clock monitor circuit may be combined with a circuit that detects narrow glitches in the monitored clock signal. Devices and systems with one or more monitored clock signals, and methods of clock signal monitoring, are also described.

Clock monitor

The control signal edges of pull-up and pull-down output transistors are aligned by a feedback system. The feedback system works to align the edges of these pull-up and pull-down control pulses while also reducing and/or minimizing any overlap of pull-up and pull-down control pulses. The feedback system uses a proportional feedback loop and an integral feedback loop. The proportional feedback loop controls the crossover voltages of the differential clock signals used to generate the pull-up and pull-down pulses. The integral feedback loop controls the crossover voltages of the differential clock signals output by the delay elements of a delay-locked loop. These crossover voltages are controlled by the feedback loops such that the edges of the pull-down control pulses are aligned to the edges of the pull-up control pulses (and vice versa) without creating excessive overlap.

Output driver pulse overlap control

Multiple, distributed, clock generating delay-locked loop (DLL) elements are interconnected/coupled in such a way as to reduce the amount of phase error present in the clocks output by these DLL elements. A plurality of DLL elements are interconnected/coupled such that a root input clock is successively relayed down a series of DLL elements. The output clocks from each of these DLL elements are interconnected/coupled to phase-corresponding output clocks from DLL elements in the series. This reduces the amount of phase error on these output clocks when compared to DLL elements that do not have outputs coupled to each other.

Distributed multi-phase clock generator having coupled delay-locked loops

Embodiments are disclosed that relate to multi-phase clock generators and data samplers for use in high speed I/O circuitry. One disclosed example provides a multi-phase clock generator including a delay line having a plurality of delay elements, the delay line being configured to receive an input clock signal and output a plurality of output clock signals having different phases compared to a phase of the input clock signal. The multi-phase clock generator further includes a control circuit configured to control the delay line based at least in part upon rising edges and falling edges of one or more output clock signals output at one or more locations along the delay line.

Multi-phase clock generation

In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, and each multiplexing drive unit including a pulse-controlled push-pull output driver having first and second inputs and an output. Each multiplexing driver unit further includes a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, wherein each of the first and second M:1 pulse-generating multiplexers has three or fewer gate delays from a clock input to an output of the pulse-generating multiplexer.

Serializing transmitter

A signal sampling system that includes N samplers is disclosed. Each sampler includes a data input having a decision logic level threshold, a plurality of offset control inputs, a plurality of offset magnitude inputs, an un-buffered output, and a buffered output. Each sampler further includes circuitry coupled between the inputs and outputs that is configured to cause a time delay from an input signal transition to an output signal transition such that, after an offset control input transitions from a first voltage to a second voltage, the decision logic level threshold changes in a time substantially less than one gate delay, and after the sample clock transitions from a first logic state to a second logic state, the un-buffered output transitions within a time substantially equal to one gate delay and the buffered output transitions within a time substantially equal to two gate delays.

Decision feedback equalization

In embodiments of a serializing transmitter, the serializing transmitter includes N multiplexing drive units, each configured to generate a series of output pulses derived from input data signals and multi-phase clock signals, and each multiplexing drive unit including a pulse-controlled push-pull output driver having first and second inputs and an output. Each multiplexing driver unit further includes a first M:1 pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, wherein each of the first and second M:1 pulse-generating multiplexers has four or fewer clock inputs.

In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.

High-speed I/O data system

In embodiments of a serializing transmitter, the serializing transmitter includes one or more multiplexing drive units that each generate a series of output pulses derived from input data signals and multi-phase clock signals. Each of the multiplexing drive units includes a pulse-controlled push-pull output driver that has first and second inputs, and an output coupled to an output of the multiplexing drive unit. Each of the multiplexing drive units also includes a first M:1 (where M is two or more) pulse-generating multiplexer having an output coupled to the first input of the pulse-controlled push-pull output driver, and generating a first series of intermediate pulses at the output; and a second M:1 pulse-generating multiplexer having an output coupled to the second input of the pulse-controlled push-pull output driver, and generating a second series of intermediate pulses at the output.

A multi-phase clock generator circuit receives an input clock signal and produces multiple output clock signal, each from a respective delay stage of a multi-stage voltage-controlled delay line (VCDL). The rising edges of the multiple output clock signals produced by the circuit are substantially equidistant in time from one another and have substantially equal phase spacing.

Multiphase clock generator with enhanced phase control

Method and apparatus for sampling a high-speed digital signal include providing a data signal to a differential data input circuit, an offset control signal, and a strobe pulse. In response to the strobe pulse, the data signal is resolved into an output logic state based to a relatively greater extent on the differential data signal and to a relatively lesser extent on the offset control signal.

High-speed data sampler with input threshold adjustment

A multi-phase correction circuit adjusts the phase relationship among multiple clock signals such that their rising edges are equidistant in time from one another.

Multi-phase correction circuit

A phase control circuit includes a signal generator sub-circuit that generates a set of phase reference signals having phase angles generally distributed over a phase angle adjustment range. A controller sub-circuit produces weighting signals that assign relative priority for each of the phase reference signals, and includes at least one incremental adjustment input. The controller sub-circuit is adapted to maintain the weighting signals in a generally steady state when receiving signaling on the adjustment input that represents no adjustment, and to adjust relative intensities of the weighting signals based on stimulation of the adjustment input. The phase control circuit further includes a mixer sub-circuit that is coupled to the set of phase reference signals and to weighting signals that collectively control a mix of the phase reference signals. The mixer sub-circuit is adapted to produce an output signal having a phase angle that is based on the mix of the phase reference signals.

Mixer-based phase control

A data sampler system receives a high-speed data stream and uses a first set of data samplers for sampling the data stream at a first set of clock phase angles to produce a first set of sequential data 'eye' samples. A second set of data samplers, to sampled at a second set of clock phase angles that are different from the first set of clock phase angles to produce a second set of sequential data transition samples. The first set of data samplers, the data stream is sampled at the second set of clock phase angles to produce a third set of sequential data transition samples and with the second set data samplers, the data stream is sampled at a first set of clock phase angles to produce a fourth set of sequential data 'eye' samples. The system alternates between the first mode and a second mode in which the results produce a reduced input offset voltage for the sampler system.

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Alan Fiedler