Silicon Laboratories Inc.

Alan F Hendrickson

David S Trager

Li Gao

Robert C Wagner

John M Khoury

Alessandro Piovaccari

Ramin Khoini-Poorfard

David P Bresemann

David Le Goff

Mitch Reid

Michael R May

Aslamali A Rafi

Marius Goldenberg

Abdulkerim Coban

Frederick Rush

Richard A Johnson

Peter Vancorenland

Michael James Mills

Ion Constantin Tesu

Mitchell Reid

Pascal Blouin

Chunyu Xin

Henry William Singor

Qi Cai

Zhongchun Liu

Jiangtao Yi

Chengming He

Jean-Marc Guyot

An integrated circuit includes a tuner, a digital television (DTV) demodulator, an analog television (ATV) demodulator, and a controller. The tuner includes an input for receiving a radio frequency (RF) signal including at least one of an analog television signal and digital television signal, and including a first output terminal and a second output terminal. The DTV demodulator includes a DTV input coupled to the first output terminal of the tuner and includes a DTV output terminal. The ATV demodulator includes an ATV input coupled to the second output terminal of the tuner and includes an ATV output terminal. The controller is coupled to the tuner, the DTV demodulator, and the ATV demodulator to configure the tuner and at least one of the DTV demodulator and the ATV demodulator for receiving television content in a selected television format.

Receiver and method of receiving analog and digital television signals

A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.

Mixed-mode receiver circuit including digital gain control

According to one aspect, a mixed-signal tuner for analog and digital TV reception incorporates a demodulator for analog TV, employing various features for resolving limitations of the analog circuitry and for achieving compatibility with various global TV standards. Such features, which may be present in one or more embodiments, include the use of a variable sample rate in all digital clocks for frequency planning, and use of a microcontroller (MCU) to control various circuitry of the tuner.

Digital signal processor (DSP) architecture for a hybrid television tuner

Techniques are disclosed relating to video signal-to-noise ratio (VSNR) measurement. In one embodiment, an analog television signal receiver includes a measurement circuit configured to measure noise in a video signal over one or more intervals that correspond to a horizontal control signal of the video signal and a control unit configured to determine a VSNR based on the measurement. In another embodiment, a first noise calculation circuit is configured to determine first noise information from a video signal and a second noise calculation circuit is configured to determine second noise information from a video signal in a manner different from the first noise calculation circuit. A control unit may be configured to generate a VSNR based on one or both of the first noise information and the second noise information.

Apparatus for measuring noise in an analog signal

In various implementations, a re-configurable phase lock loop may have multiple signal paths, including a feedforward path to operate in a carrier frequency acquisition mode to obtain a carrier frequency estimate and a feedback loop path to operate in a carrier frequency tracking mode to translate an incoming signal to a baseband signal. The multiple signal paths may share most of the hardware to reduce implementation cost.

Digital phase lock loop configurable as a frequency estimator

Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database. For example, one or more analog control signals can be generated using resistor circuits for which specific selectable resistor configurations map to particular information stored in a look-up table or other database structure within the integrated circuit. The analog control signals are converted to digital values within the integrated circuit, and these digital values are used to select device information from the on-chip database. Furthermore, the selected device information can be stored in on-chip device information registers. And the digital values themselves can be stored and used as identification, configuration or other device information.

Resistor identification configuration circuitry and associated method

A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is coupled to an input of the first driver. The gain of at least one of the first and second drivers is adjusted until a calibration signal (V) present at the input of the first driver is substantially the same as a calibration signal (V) present at the input of the second driver.

Longitudinal balance calibration for a subscriber line interface circuit

According to a disclosed method, a calibration signal is provided at a first frequency corresponding to a low frequency edge of a desired passband to an input of a filter (). A first value is measured at an output of the filter (). The calibration signal is provided at a second frequency corresponding to a high frequency edge of the desired passband to the input of the filter (). A second value is measured at the output of the filter (). The first value is compared to the second value. A characteristic of the filter () is changed in response to the comparing. In one form, the filter is an IF filter () and a receiver () includes both the IF filter () and a calibration circuit () for forming the calibration signal and providing the calibration signal to the IF filter to change the characteristic in response to a calibration operation.

Method and apparatus for calibrating a filter of a receiver

An integrated circuit device and associated method are disclosed utilizing on-chip programmable circuitry that receives and stores vendor identification information, in particular, for devices meeting operational requirements of the Audio CODEC '97 Component Specification. The programmable circuitry allows for vendor ID information for multiple device configurations and/or multiple vendor supplied devices to be accurately reported to external devices. In particular, direct-access-arrangement (DAA) circuitry is disclosed having such on-chip programmable circuitry that may be loaded with vendor identification information at least in part from an external source. The external source may in turn be programmable circuitry, such as a EEPROM. This disclosed invention allows a single hardware DAA solution to be utilized by different software vendors, who each add their own respective software functionality, and to be utilized by a single software vendor, who desires to bundle different software functionality or revisions with the single hardware DAA solution. In this way, an integrated circuit may be designed and manufactured to provide a single hardware solution for a variety of different software or other programmable configurations.

Programmable vendor identification circuitry and associated method

Caller ID (CID) data-reporting circuitry operates in conjunction with direct-access arrangement (DAA) circuitry or other circuitry that operates within the operational requirements of the Audio Codec '97 (AC-97) Component Specification. The CID data-reporting circuitry provides for the transfer of a data word from the DAA circuitry to a host computer or controller that operates within the AC-97 operational specifications. The CID data-reporting circuitry transfers the CID data in an asynchronous manner, i.e., at non-pre-determined intervals. Software running on the host computer or the controller may thus examine each data word or group of data words and take appropriate action, for example, process the data further or terminate the data transfer. A command interpreter begins the data transfer by initializing an address pointer used to facilitate retrieving the data from a CID random-access memory (RAM) and to make the data available to the host computer or controller through an output register.

Growing community of inventors

Rollingwood, TX, United States of America

Alan F Hendrickson