Advanced Micro Devices Corporation

Dsp Group Limited

Sony Corporation

Amd Inc.

Dps Group, Inc.

Alan F Hendrickson

Joseph W Peterson

Herbert M Chen

Dale E Gulick

John G Bartkowiak

Jacqueline E Mullins

Peter E Sheldon

Ken M Tallo

Paul G Schnizlein

Alfredo R Linz

Munehiro Yoshikawa

Carlin D Cabler

Rajiv M Hattangadi

Kazushige Tsurumi

Stephen T Janesch

Hiroshi Matsubara

Dean Grumlose

Bruno Damien

In a digital communication receiver, a system and method for recovering the timing of frames in the received signal. The receiver synchronizes an internal frame clock with a series of received data frames in the received data stream. One embodiment of a method for performing the frame synchronization proceeds by first recovering a symbol timing for data symbols in the received frames, then acquiring a frame timing by scanning the received data symbols for the SYNC field only during a narrow detection window around an expected location in time for the SYNC field, and then locking the frame timing. An embodiment of a system for performing the frame synchronization comprises an input for receiving the data frames in the received data stream, a symbol clock that indicates symbol transitions in the received data stream, timing logic that indicates the detection window during which the a SYNC field is expected, a SYNC-field detector, and a receiver frame clock.

Frame synchronization in a digital communications system

In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment of the method, the receiver waits for detection of a SYNC field to confirm at least a coarse synchronization or the receiver's local PN sequence with the received PN sequence (in the received signal). The receiver then performs a fast tracking to finely synchronize the receiver's PN sequence with the received PN sequence, preferably for a fixed duration of time. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, an ML detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal, and a fast-tracking logic. The fast-tracking logic temporarily advances and temporarily delays the receiver PN clock by a small shift and measures the resulting correlations between the receiver's PN sequence and the received PN sequence. If the advanced correlation is greater or less than the delayed correlation, then the fast-tracking logic accordingly makes a small adjustment to advance or delay the receiver PN clock. This temporary advancing, temporary delaying, and adjusting of the receiver PN clock is preferably repeated a fixed number of times.

Fast tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system

In a direct sequence spread spectrum communication system, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the communication system is a time-division duplexing (TDD) or a time-division multiple-access (TDMA) system. A receiver in the communication system uses a &ldquo;sliding correlator&rdquo; maximal-likelihood (ML) detection system to scan through a range of possible PN phases to determine the correct one. In one embodiment of a method for performing the synchronization, a receiver acquires the PN phase by repeating the ML detection for a time greater than or equal to the period of the TDD or TDMA frames, with a sufficiently high repetition rate to ensure that the correct PN phase is examined at least once during a received frame. The acquisition is thereby completed within a fixed amount of time. One embodiment of a system for performing the synchronization includes an input for the received signal, a receiver PN clock, and an ML detection logic. The ML detection logic repeats the ML detection so that at least one complete set of PN phases is examined during a time when the received signal is active. In another embodiment of the method, the receiver acquires the PN phase by performing the ML detection during a timeslot in which a received frame is expected. Again, the acquisition is completed within a fixed amount of time.

Rapid acquisition of PN synchronization in a direct-sequence spread-spectrum digital communications system

In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, a receiver PN clock, and a slow-tracking logic. The slow-tracking logic temporarily advances and delays the receiver PN clock by a small shift and checks if either advancing or delaying consistently results in improved correlations. If so, the slow-tracking logic adjusts the receiver PN clock accordingly. The slow tracking logic preferably also includes a counter that maintains an integrated total of the adjustments to the receiver clock. The integrated total adjustment is used to determine the long-term adjustment.

Slow tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system

In a digital communications receiver, a system and method for evaluating the quality of received symbols and for initializing and adjusting a symbol clock. The invention presents a symbol quality detector that evaluates symbols which have been received by the receiver and detected in a matched filter. The received symbols are members of a constellation with elements that have purely I or purely Q components. The symbol-quality detector comprises inputs that receive the I and Q components of the symbols, and a logic block that generates the symbol-quality signal by constructing the quantity &verbar;&verbar;I&verbar;&minus;&verbar;Q&verbar;&verbar;. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The present invention further comprises a digital communications receiver that uses a symbol-quality detector to evaluate its symbol clock. Still further, the present invention contemplates a method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. In this embodiment of the invention, the receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The method then determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

Symbol-quality evaluation in a digital communications receiver

A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.

Phase detector for carrier recovery in a DQPSK receiver

In a digital communication system for voice signals, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for direct-sequence spreading and despreading of the communicated signals. In one embodiment, a received signal is a time-division duplexing (TDD) or time-division multiple access (TDMA) signal, and a receiver performs a complete 'sliding correlator' examination of the received signal in a fixed time by using the timing of the TDMA or TDD frames. This examination allows a rapid initial acquisition of the PN synchronization. In another embodiment of the receiver, the initially acquired PN phase is verified by reading a SYNC field from the received signal and by checking that shifting the receiver's local PN phase results in a degraded correlation between the local PN sequence and the received signal. A fast tracking procedure finely synchronizes the receiver's PN sequence with the received PN sequence by repeatedly testing the effects of dithering the receiver's PN phase. The fast tracking is preferably performed for a fixed duration of time and is followed by a slow tracking that continues the dithering to maintain the fine synchronization. In the slow tracking procedure, the receiver preferably adjusts its PN phase only if repeated tests consistently indicate a lag or lead in the synchronization. The slow tracking procedure preferably also includes a second-order correction in the PN phase to allow for frequency differences between a PN clock in the receiver and a PN clock in a remote transmitter.

Timing recovery for a pseudo-random noise sequence in a direct-sequence

In a direct sequence spread spectrum digital communication receiver, a system and method for recovering and verifying the timing or phase of a pseudo-random noise (PN) sequence used for despreading received signals. In one embodiment, the method includes steps of: (a) determining an initial value of a received PN phase, (b) setting the receiver's PN phase equal to the initial value of the received PN phase, (c) a first testing to verify that the receiver identifies a SYNC field within a testing time of predetermined duration, (d) a second testing, to verify that temporarily shifting the receiver's PN phase results in a degraded correlation between the receiver's PN sequence and the received signal, and (e) repeating steps (a)-(d) if either of the testings indicate that the receiver's PN sequence is not correct. One embodiment of a system for recovering and verfying the PN timing includes an input for receiving a received spread-spectrum data stream, a maximal likelihood detection logic, a receiver PN clock, a despreading mixer that generates a narrowband signal from the spread-spectrum data stream, a first testing logic that generates a PASS output if it identifies a SYNC field in the narrowband signal during a testing period, and a second testing logic that temporarily shifts the receiver PN clock and generates a PASS output if the temporary shifting degrades the correlation between the receiver's PN sequence and the received signal.

Verification of PN synchronization in a direct-sequence spread-spectrum

A system for recognizing degraded pseudo-random noise (PN) synchronization in a spread-spectrum receiver. The system uses a signal that indicates the correlation of the locally generated PN sequence with the received PN sequence. The correlation signal can be a symbol-length integration of the output from a square-law detector, or an appropriate similar signal. If the correlation signal is not degraded by demodulating with a deliberately shifted copy of the PN sequence, there is an indication that the unshifted PN sequence was itself not correctly synchronized. A sufficiently degraded correlation signal indicates that the receiver's PN synchronization is correct. To prevent the loss of transmitted data during the testing, each transmitted frame contains a Measurement field (that contains no payload data) for assessing the synchronization in this manner. The PN sequence is shifted only during this specific portion of the received frame.

Verification of PN synchronization in a spread-spectrum communications

Disclosed is a system for selectively enabling intermediate data processing of digital signals external to an integrated circuit (IC). The system comprises a transcoder, a codec connected to the transcoder, and a data processor located externally to the IC. In response to a strobe signal, a programmable switch diverts digital signals between the transcoder and the codec to a data path from the IC to the external processor. The digital signals are formatted within the IC for processing by the external processor. The externally processed digital signals are returned to the IC via a data path from the external processor. The digital signals are then reformatted within the IC for further processing by the IC.

Method and apparatus for external intermediate data processing

A method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. The receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The received symbols are members of a constellation with elements that have purely I or purely Q components. A symbol-quality signal is generated by constructing the quantity .vertline..vertline.I.vertline.-.vertline.Q.vertline..vertline.. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The method determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

Method for compensating filtering delays in a spread-spectrum receiver

Method and apparatus for providing a FSK data slicer for use in wireless telecommunications such as cordless telephones. The FSK data slicer is used by a receiver circuit in a wireless telecommunication device for converting an analog data signal to a digital data signal. Furthermore, the FSK data slicer responds to different mode of the analog data signal. The FSK data slicer includes a low-pass filter, a controller, a comparator, and an integrator. The low-pass filter receives the analog data signal for generating a median voltage, or slice voltage. Furthermore, the low-pass filter includes connectors to allow an external resistor to be serially connected between the filter input and the analog data signal and to allow an external capacitor to be connected in parallel with the slice voltage at the filter output. The bandwidth of the low-pass filter is controlled by the controller. The controller responds to specific intervals of the TDD frames, initial acquisition of data in the analog data signal, and known characteristics of the TDD frames and adjusts the low-pass filter bandwidth, accordingly. As a result, the low-pass filter drives the slice voltage only when it can do so accurately, and drives it strongly when the slice voltage will be very accurate. The comparator receives and compares the analog data signal and the slice voltage in order to produce a digital data signal. The digital data signal is then sent to the integrator, which over-samples each data bit of the digital data signal. The over-sampling is concentrated on the middle three quarters of each data bit, thereby ensuring the highest level of reliability.

Data slicer for demodulated binary FSK signals in a time division duplex

A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.

Threshold voltage level generator for time division duplex communications

A communication circuit designed to be coupled to a radio receiver so as to receive a data signal and a receive signal strength indicator signal indicative of radio carrier strength therefrom, and further designed to be coupled to a controller, the communications circuit including a first, second, third, and fourth subcircuit. The first subcircuit receives the receive signal strength indicator from the receiver, determines radio carrier strength therefrom, and transfers the determined strength information to the controller. The second subcircuit receives the data signal from the receiver, determines if there are bit error within that signal, and transfers its determinations to the controller. The third subcircuit receives the data signal from the receiver, determines if there is jitter therein, and transfers its determinations to the controller. The fourth subcircuit is coupled to the second and third subcircuits to receive the output thereof, and is further coupled to the controller so as to receive output therefrom, the fourth subcircuit acting in response to the outputs to suppress signal noise.

Receiver quality measurement system for use in digital cordless

A method and apparatus for radio frequency (RF) link establishment is disclosed. The method and apparatus uses messages with a set data field containing N-bit channel markers and synchronization words for link establishment and monitoring. The present invention allows for correct detection of the initial channel marker even if less than N bits are received correctly.

Growing community of inventors

Austin, TX, United States of America

Alan F Hendrickson