National Semiconductor Corporation

Texas Instruments Corporation

Alan Erik Segervall

Mahalingam Nandakumar

Sumantra Seth

Muhammad Yusuf Ali

Varadarajan Devnath

Ross Anthony Pimentel

Luu Thanh Nguyen

Jitendra Mohan

Robert Callaghan Taft

Laurence Douglas Lewicki

James B Wieser

Vijaya G Ceekala

Stephen Gee

As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

Integrated ESD event sense detector

An electronic device, e.g. integrated circuit, has an n-type region and a p-type region located within a semiconductor substrate, the n-type region and the p-type region each intersecting the substrate surface. A dielectric structure is located directly on the substrate surface. The dielectric structure has first and second laterally opposed sides, with the first side located over the n-type region and the second side located over the p-type region.

Dielectric spaced diode

An electronic device, e.g. an integrated circuit, is formed on a P-type lightly-doped semiconductor substrate having an N-type buried layer. First and second N-wells extend from a surface of the substrate to the buried layer. A first NSD region is located within the first N-well, and a second NSD region is located within the second N-well. A PSD region extends from the substrate surface into the substrate and is located between the first and second NSD regions. A P-type lightly-doped portion of the substrate is located between the N-well and the substrate surface and between the PSD region and the first and second NSD regions.

A serial communication interface driver is provided wherein current steering switches are also used to provide termination impedances. The output voltage can be produced by a voltage-dividing current path between two regulated voltages, which provides improved efficiency.

Voltage mode serial interface driver with PVT compensated impedance

A tunable impedance circuit is provided wherein at least one of a plurality of impedance elements is combined with at least another of the plurality of impedance elements to produce a composite impedance. A control voltage is used to determine how many of the impedance elements are to be combined to produce the composite impedance. A current that is substantially invariant over a range of operating conditions is caused to flow through a control impedance to produce the control voltage.

Tuning control for a PVT-compensating tunable impedance circuit

A system and method is provided for providing power managed common mode logic (CML) transmitters for use with main and auxiliary power sources. Power switch circuitry comprising two PMOS transistors switches the CML transmitter output circuit between a main power source node (VDD) and an auxiliary power source node (TXRAIL). A bias circuit biases the two PMOS transistors to place the main power source voltage on the auxiliary power source node (TXRAIL) when the value of the main power source voltage is nonzero. The bias circuit also biases the two PMOS transistors to remain off when the value of the main power source voltage on the main power source node (VDD) is zero.

System and method for providing power managed CML transmitters for use with main and auxiliary power sources

A system and method is disclosed for providing a fast turn on bias circuit that permits a fast transition from an idle 'power down' state to an active 'power up' state in current mode logic (CML) transmitter output circuits. The invention comprises a capacitor coupled to a bias transistor and a charge switch circuit for controlling the operation of the capacitor. The capacitor has a value of capacitance that is equal in magnitude and opposite in sign to the Miller coupling capacitance in the bias transistor. The capacitor compensates for the Miller coupling capacitance within the bias transistor in less than ten nanoseconds. This permits a CML transmitter to more quickly restart the transmission of data after an active state has been initiated.

System and method for providing a fast turn on bias circuit for current mode logic transmitters

The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.

Electrical interconnect with minimal parasitic capacitance

The pads of a semiconductor die are protected from an electrostatic discharge (ESD) event by an ESD protection circuit that has a number of master corner clamps and a number of slave clamps that are controlled by the master corner clamps. The slave clamps are formed under the ESD plus and minus rings which, in turn, are formed under the pads, thereby providing a significant reduction in the height of the I/O cell, and improved ESD performance by reducing metalization IR drops.

Fully distributed slave ESD clamps formed under the bond pads

An electrostatic discharge (ESD) corner clamp is connected to a positive ESD rail that has a steady first voltage, such as 2.6V, and can be driven to a larger second voltage, such as 4.3V. The ESD corner clamp provides 5V tolerance by utilizing a keep off circuit that prevents the corner clamp from triggering when the voltage on the positive ESD rail changes from the first voltage to the second voltage.

5V tolerant corner clamp with keep off circuit

The pads of a semiconductor die are protected from an electrostatic discharge (ESD) event by an ESD protection circuit that has a number of master clamps and a number of slave clamps that are controlled by the master clamps. The slave clamps are formed under the ESD plus and minus rings which, in turn, are formed under the pads, thereby providing a significant reduction in the height of the I/O cell, and improved ESD performance by reducing metalization IR drops. The master and slave clamps provide 5V tolerance by utilizing a keep off circuit that prevents the master clamp from triggering when the voltage on the positive ESD rail changes from a first non-ESD voltage to a second non-ESD voltage.

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Half Moon Bay, CA, United States of America

Alan Erik Segervall