Fairchild Semiconductor Corporation

Alan Elbanhawy

Christopher Boguslaw Kocon

Steven Paul Sapp

Ashok Challa

Peter H Wilson

Babak S Sani

Dean E Probst

Bruce Douglas Marchant

James J Murphy

Becky Losee

Robert Herrick

Gordon K Madson

Debra S Woolsey

Benny Tjia

A method can include forming a drift region, forming a well region above the drift region, and forming an active trench extending through the well region and into the drift region. The method can include forming a first source region in contact with a first sidewall of the active trench and a second source region in contact with a second sidewall of the active trench. The method also includes forming a charge control trench where the charge control trench is aligned parallel to the active trench and laterally separated from the active trench by a mesa region, and where the portion of the well region is in contact with the charge control trench and excludes any source region. The method also includes forming an oxide along a bottom of the active trench having a thickness greater than a thickness of an oxide along the first sidewall of the active trench.

Methods related to power semiconductor devices with thick bottom oxide layers

A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region and into the drift region, a charge control trench extending deeper into the drift region than the active trench, an oxide film that fills the active trench, the charge control trench and covers a top surface of the substrate, an electrode in the active trench, and source regions. The method also includes etching the oxide film off the top surface of the substrate and inside the active trench to leave a substantially flat layer of thick oxide having a target thickness at the bottom of the active trench.

Methods of making power semiconductor devices with thick bottom oxide layer

A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region. The active trench, which includes sidewalls and bottom lined with dielectric material, is substantially filled with a first conductive layer and a second conductive layer. The second conductive layer forms a gate electrode and is disposed above the first conductive layer and is separated from the first conductive layer by an inter-electrode dielectric material. The device also includes source regions having the first conductivity type formed inside the well region and adjacent the active trench and a charge control trench that extends deeper into the drift region than the active trench and is substantially filled with material to allow for vertical charge control in the drift region. The charge control trench can be lined with a layer of dielectric material and substantially filled with conductive material. The active trench can include a second shield electrode made of conductive material disposed below the first shield electrode. The first conductive layer inside the active trench can form a secondary gate electrode that is configured to be electrically biased to a desired potential. The semiconductor device can also include a Schottky structure formed between the charge control trench and a second adjacent charge control trench.

Trenched shield gate power semiconductor devices and methods of manufacture

A chip module is disclosed. It includes a circuit substrate, a semiconductor die comprising a power transistor mounted on the circuit substrate, and a passive electronic component. The passive electronic component is in electrical communication with the semiconductor die, and is in thermal communication with the semiconductor die.

Chip module for complete power train

In one embodiment, a power converter system includes a switching circuitry having a plurality of switches operable to be turned on and off to cause current to flow to deliver power to a load. A driver circuitry is responsive to an oscillation signal and generates control signals for turning on and off the switches in the switching circuitry. A free-running oscillator circuitry provides the oscillation signal to the driver circuitry. The free-running oscillator circuitry has an operational amplifier. A frequency of the oscillation signal will be higher if the operational amplifier outputs a first value, and the frequency of the oscillation signal will be lower if the operational amplifier outputs a second value.

Synchronous buck power converter with free-running oscillator

Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

Power semiconductor devices and methods of manufacture

Semiconductor devices containing a MOSFET and an on-chip current sensor in the form of a magnetic resistive element are described. The magnetic resistive element (MRE) is proximate the MOSFET in the semiconductor device. The current flowing through the MOSFET generates a magnetic field that is detected by the MRE. The MRE comprises a metal film that is placed proximate the MOSFET during the normal fabrication processes, thereby adding little to the manufacturing complexity or cost. Using the MRE adds an accurate, effective, and cheap method to measure currents in MOSFET devices.

Semiconductor devices containing on-chip current sensor and methods for making such devices

A method of driving a dual-gated MOSFET having a Miller capacitance between the MOSFET gate and drain includes preparing the MOSFET to switch from a blocking mode to a conduction mode by applying to the MOSFET shielding gate a first voltage signal having a first voltage level. The first voltage level is selected to charge the Miller capacitance and thereby reduce switching losses. A second voltage signal is applied to the switching gate to switch the MOSFET from the blocking to the conduction mode. The first voltage signal is then changed to a level selected to reduce the conduction mode drain-to-source resistance and thereby reduce conduction losses. The first voltage signal is returned to the first voltage level to prepare the MOSFET for being switched from the conduction mode to the blocking mode.

Method of driving a dual gated MOSFET

A method for reducing miller capacitance and switching losses in an integrated circuit includes providing a switching gate electrode having respective portions that are coplanar with the source and well regions of the integrated circuit. The switching gate electrode is configured for switching the integrated circuit on and off in response to a relatively small change in applied voltage. A shielding gate electrode is formed with respective portions coplanar with the switching electrode and the well region. The shielding electrode is configured for charging the gate-to-drain overlap region of the integrated circuit.

Method for improved MOS gating to reduce miller capacitance and switching losses

In accordance with the present invention, a switching converter includes two transistors Qand Qparallel-connected between two terminals. Transistor Qis optimized to reduce the dynamic loss and transistor Qis optimized to reduce the conduction loss. Qand Qare configured and operated such that the dynamic loss of the converter is dictated substantially by Qand the conduction loss of the converter is dictated substantially by Q. Thus, the tradeoff between these two types of losses present in conventional techniques is eliminated, allowing the dynamic and conduction losses to be independently reduced. Further, the particular configuration and manner of operation of Qand Qenable reduction of the gate capacitance switching loss when operating under low load current conditions.

Method and circuit for reducing losses in DC-DC converters

A gate structure for a semiconductor device includes a shielding electrode and a switching electrode. Respective portions of the shielding electrode are disposed above said drain region and said well region. A first dielectric layer is disposed between the shielding electrode and the drain and well regions. The switching electrode includes respective portions that are disposed above said well region and said source region. A second dielectric layer is disposed between the switching electrode and the well and source regions. A third dielectric layer is disposed between the shielding electrode and the switching electrode.

Method and apparatus for improved MOS gating to reduce miller capacitance and switching losses

Method of and apparatus for driving a dual gated MOSFET

An apparatus for and method of achieving current balancing among phases of a multi-phase power supply by reducing and controlling the temperature variation among packages disposed within each phase. Each package contains a dc-to-dc converter (e.g. a buck converter), a temperature sensor and may also contain a driver, which supplies a pulse train for driving the converter. By controlling the temperature among phases to within &plusmn;X % a balancing of currents among phases to within &plusmn;X/2 % is achieved.

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Hollister, CA, United States of America

Alan Elbanhawy