Ppg Industries Ohio, Inc.

Ppg Industries, Inc.

Basf Corporation

Hewlett-packard Company

Alan E Wang

Kevin C Olson

William C Allison

Robert H Tang

Louis J Nehmsmann

Robert G Swisher

Thomas H Di Stefano

Michael O Okoroafor

Suk H Cho

Huawen Li

Gregory J McCollum

Suryya K Das

Steven R Zawacky

Thomas C Moriarity

Michael G Sandala

Peter Elenius

Yingchao C Zhang

William H McDonald

Thomas W Goodman

Thomas H DiStefano

Michael J Pawlik

Bulent E Yoldas

Craig A Wilson

Robert A Montague

Cheruthur Govindan

Robert G Briody

Donald P Hart, Jr

Charles T Hill

George D Morris

Amy E Doty

Richard W Morales

A method includes forming a first substrate by (a) applying an electrodepositable dielectric coating onto a conductive surface; (b) curing the dielectric coating; (c) depositing an adhesion layer and a seed layer onto the dielectric coating; (d) applying a layer of a first removable material to the seed layer; (e) forming openings in the first removable material to expose areas of the seed layer; (f) electroplating a first conductive material to the exposed areas of the seed layer; (g) applying a layer of a second removable material; (h) forming openings in the second removable material to expose areas of the first conductive material; (i) plating a second conductive material to the exposed areas of the first conductive material; (j) removing the first and second removable materials; (k) removing unplated portions of the seed layer; repeating steps (a) through (k) to form a second substrate; and laminating the first and second substrates together with a layer of dielectric material between the first and second substrates to form at least one interconnect between the first and second substrates.

Method of forming solid blind vias through the dielectric coating on high density interconnect (HDI) substrate materials

A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Printed circuit board with improved via design

A circuit board or each circuit board of a multi-layer circuit board includes an electrically conductive sheet coated with an insulating top layer covering one surface of the conductive sheet, an insulating bottom layer covering another surface of the conductive sheet and an insulating edge layer covering an edge of the conductive sheet. An insulating interlayer can be sandwiched between a pair of adjacent circuit boards of a multi-layer circuit board assembly. A landless through-hole or via can extend through one or more of the circuit boards for connecting electrical conductors on opposing surfaces thereof.

Method of forming a circuit board with improved via design

A method is provided comprising: coating an electrically conductive core with a first removable material, creating openings in the first removable material to expose portions of the electrically conductive core, plating a conductive material onto the exposed portions of the electrically conductive core, coating the conductive material with a second removable material, removing the first removable material, electrophoretically coating the electrically conductive core with a dielectric coating, and removing the second removable material.

Method of forming solid blind vias through the dielectric coating on high density interconnect substrate materials

A process for fabricating a circuit board includes: providing a substrate including a first electrically conductive core having a first insulating coating on a first side and a second insulating coating on a second side, forming an opening in the first and second insulating coatings and the first electrically conductive core, exposing an edge of the conductive core within the opening, and electrodepositing a third insulating material on the exposed edge of the first electrically conductive core. A circuit board fabricated using the process is also provided.

Process of fabricating a circuit board

Method of forming a printed circuit board with improved via design

Provided is a method of forming a circuit board including (a) providing a first conductive sheet; (b) selectively removing one or more portions of the first conductive sheet to form a first panel having a first circuit board that is coupled to a disposable part of the first panel by at least one tab that extends from an edge of the first circuit board to an edge of the disposable part of the first panel; (c) applying an insulating coating to the first circuit board so that at least each edge of the first circuit board is covered thereby; and (d) separating the first circuit board from the disposable part in a manner whereupon at least part of the tab remains attached to the first circuit board and includes an exposed edge of the conductive sheet of the first circuit board. Circuit boards formed by the method are also provided.

Circuit board and method of manufacture thereof

Single or multi-layer printed circuit board with improved via design

The present invention relates to an article for altering a surface of a workpiece, or a polishing pad having a window. In particular, the polishing pad includes a polyurethane urea material wherein the polyurethane urea material contains cells which are at least partially filled with gas. The polyurethane urea material can be prepared by combining polyisocyanate and/or polyurethane prepolymer, hydroxyl-containing material, amine-containing material and blowing agent. The polishing pad according to the present invention is useful for polishing articles, and is especially useful for chemical mechanical polishing or planarization of microelectronic and optical electronic devices such as but not limited to semiconductor wafers. The window of the polishing pad is at least partially transparent and thus, can be particularly useful with polishing or planarizing tools that are equipped with through-the-platen wafer metrology.

Polyurethane urea polishing pad

Processes for fabricating a multi-layer circuit assembly and a multi-layer circuit assembly fabricated by such processes are provided. The process includes (a) providing a substrate at least one area of which comprises a plurality of vias, these area(s) having a via density of 500 to 10,000 holes/square inch (75 to 1550 holes/square centimeter); (b) applying a dielectric coating onto all exposed surfaces of the substrate to form a conformal coating thereon; and (c) applying a layer of metal to all surfaces of the substrate. Additional processing steps such as circuitization may be included.

Process for fabricating a multi layer circuit assembly

Method of making a circuit board

A pigmented curable composition adapted for decorating ceramic substrates (e.g., glass bottles) comprises curable organic binder and solid spherical particles (glass or polymer) having diameters of 10 to 50 microns for facilitating overprinting of additional layers. The preferred embodiment comprises: (a) reactive organic resin component in which epoxy groups comprise the major reactive functionality; (b) amino-functional curing agent; (c) blocked polyisocyanate; and (d) 5 to 35 percent solid spherical particles having diameters of 10 to 50 microns.

Method and compositions for applying multiple overlying organic pigmented decorations on ceramic substrates

A polishing pad is described as comprising, (a) particulate polymer which can be chosen from particulate thermoplastic polymer (e.g., particulate thermoplastic polyurethane), particulate crosslinked polymer (e.g., particulate crosslinked polyurethane and/or particulate crosslinked polyepoxide) and mixtures thereof; and (b) organic polymer binder (e.g., polyurethane binder and/or polyepoxide binder), which can bind the particulate polymer together, wherein said organic polymer binder can be prepared in-situ. The particulate polymer and organic polymer binder can be distributed substantially across the work surface the polishing pad, and the pad can have a percent pore volume of from 2 percent by volume to 50 percent by volume, based on the total volume of said polishing pad.

Polishing pad

Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

Process for fabricating circuit assemblies using electrodepositable dielectric coating compositions

A circuit board layerin accordance with the present invention includes a conductive sheetsandwiched between an insulating top layerand an insulating bottom layer. The top and bottom layersandand the conductive sheetdefine the circuit board layerhaving an edge that includes an edgeof the conductive sheet. An insulating edge layercovers substantially all of the edgeof the conductive sheet

Single or multi-layer printed circuit board with recessed or extended breakaway tabs and method of manufacture thereof

Growing community of inventors

Gibsonia, PA, United States of America

Alan E Wang