Hrl Laboratories, LLC

Telasic Communications, Inc.

Alan E Reamon

Lloyd Frederick Linder

Peter Petre

Jose Cruz-Albrecht

Zhiwei A Xu

Yen-Cheng Kuan

Donald A Hitko

James H Schaffner

Keyvan R Sayyah

Hyok Jae Song

Jeong-sun Moon

Joseph S Colburn

Pamela R Patterson

Erick M Hirata

Keerti S Kona

Susan L Morton

Randall White

Ining Ku

Nick Elmi

A reconfigurable electro-magnetic tile includes a laser layer including a plurality of lasers, and a pixelated surface comprising a plurality of metal patches and a plurality of switches, wherein each respective switch of the plurality of switches is in a gap between a first respective metal patch and a second respective metal patch, wherein each respective switch is optically coupled to at least one respective laser of the plurality of lasers, and wherein each switch of the plurality of switches comprises a phase change material.

Reconfigurable electromagnetic surface of pixelated metal patches

An asynchronous pulse domain to synchronous digital domain converter for converting pulse domain signals in an input asynchronous pulse domain data stream to synchronous digital domain signals in a data output stream. The converter comprises a plurality of counters arranged in a ring configuration with only one counter in the ring being responsive at any given time to positive and negative going pulses in the input asynchronous pulse domain data stream, each counter, when so responsive, counting a number of time units between either (i) a positive going pulse and an immediately following negative going pulse or (ii) a negative going pulse and an immediately following positive going pulse, the counts of the counters when so responsive being synchronously converted to synchronous digital domain signals in the data output stream. The disclosed asynchronous pulse domain to synchronous digital domain converter can be used with spike domain signals if desired.

Asynchronous pulse domain to synchronous digital domain converter

A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.

Dual edge pulse de-multiplexer with equalized path delay

Multi-layer metal-shielded monolithic transmission lines are formed in side-by-side arrangement by depositing parallel planar thin film, conductive layers, separated by nonconductive separator layers to form a stack of alternating conductive and nonconductive layers. The conductive layers form a top and a bottom conductive plane and establish a mutually registered selected width of the stack. A center conductive layer has laterally spaced apart conductive strips separated by nonconductive spacer layers. The two laterally terminal of the conductive strips are spaced at the selected width. Each of the nonconductive separator layers provides a plurality of elongated vias between the two lateral terminals of the three conductive strips and the conductive planes. The vias are filled as each next metal deposition is applied for electrically interconnecting the conductive strips and planes so as to form a monolithic conductive shield about the centermost signal carrying conductor of the three conductive strips, providing electrical isolation in a coaxial arrangement.

On-chip multilayer metal shielded transmission line

A unit cell including a substrate; an active circuit disposed on the substrate; and an arrangement disposed on the substrate for routing a plurality of conductors thereover. In the illustrative implementation, the routing arrangement includes first, second and third ground planes disposed on the substrate, a first layer of conductors disposed between the first and second planes, and a second layer of conductors disposed between the second and the third planes. Each cell is adapted to connect to a device such as a detector. The inventive unit cell enables an improved focal plane array design with a smaller unit cell supporting smaller detector sizes. Smaller detector pitch allows higher density detector arrays. The inventive fan-out approach allows for complicated circuitry to be located outside the array. This permits the utilization of more sophisticated analog signed processing, such as a multiple sample approach. Multiple sampling results in a much more accurate digital Gaussian curvefit, which increases the range and intensity accuracy of readout electronics.

Unit cell with fan-out for large focal plane arrays with small detector pitch

Growing community of inventors

Woodland Hills, CA, United States of America

Alan E Reamon