International Business Machines Corporation

Alan Dziedzic

Mark Alan Lavin

Dennis Merton Newns

Gustavo Enrique Tellez

Daniel Nelson Maynard

Richard Gerard Burda

Wilm Ernst Donath

Archibald John Allen

Eric Ted Dickstein

A system for dispatching a plurality of semiconductor lots among a plurality of tools is provided. The system includes a dispatch server manager and a dispatch integrator and display device. The dispatch integrator and display device conveys a dispatch request to the manager and receives a dispatch list from the manager. The manager queries for a processing status of the plurality of semiconductor lots and displays a dispatch list in response to the processing status. The dispatch list includes an associated reason and/or code related to the processing status.

System for dispatching semiconductors lots

A method of computing a manufacturing yield of an integrated circuit having device shapes includes sub-dividing the integrated circuit into failure mechanism subdivisions (each of the failure mechanism subdivisions includes one or more failure mechanism and each of the failure mechanisms includes one or more defect mechanisms), partitioning the failure mechanism subdivisions by area into partitions, pre-processing the device shapes in each partition, computing an initial average number of faults for each of the failure mechanisms and for each partition by numerical integration of an average probability of failure of each failure mechanism, (the numerical integration produces a list of defect sizes for each defect mechanism, and the computing of the initial average includes setting a maximum integration error limit, a maximum sample size for a population of each defect size, and a maximum number of allowable faults for each failure mechansim), and computing a final average number of faults for the integrated circuit by iterativelly reducing a statistical error of the initial average number of faults for each of the failure mechanisms until the statistical error is below an error limit.

Method for prediction random defect yields of integrated circuits with accuracy and computation time controls

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Alan Dziedzic