Omnivision Technologies, Inc.

Texas Instruments Corporation

Sun Microsystems, Inc.

Alan Dean Martin

Edward Nabighian

Yi Qin

Robert Calvin Cyphers

Han Y Ko

Marc Edric Davis-Marsh

Tomonori Hirai

Ward Zhang

Keith Y Oka

A discrete field coupled capacitor with a cross-connected capacitor-pair, such as for use as a discrete bypass capacitor. The FCC includes a first port with first and second terminals, and a second port with third and fourth terminals. A first capacitor structure is connected between the first and second terminals, and a second capacitor structure connected between the third and fourth terminals. A cross-connect structure includes a first cross-connection to connect the first terminal to the third terminal, and a second cross-connection to connect the second terminal to the fourth terminal, to cross-connect the first and second capacitor structures. The capacitor structures have respective parasitic ESL, and can be disposed in proximity to effect a pre-defined ESL field coupling with reverse phasing to reduce parasitic ESL. The FCC can be constructed as a PCB or monolithic device. In a PCB four-layer construction, the cross-connections can be formed on respective mid-layers.

Discrete capacitor structure

A method for manufacturing a stepped spacer wafer for a wafer-level camera includes a step of measuring a plurality of focal lengths fof a respective one of a plurality of lenses Lof a lens wafer. The method also includes a step of fabricating a stepped spacer wafer including (i) a plurality of apertures Atherethrough, and (ii) a plurality of thicknesses Tdefining a respective thickness of the stepped spacer wafer at least partially surrounding a respective one of the plurality of apertures A. Each of the plurality of thicknesses Tis equal to a difference between (a) a respective one of the plurality of focal lengths f, and (b) a uniform thickness that is the same for each of the plurality of thicknesses.

Lens wafer assembly and associated method for manufacturing a stepped spacer wafer

Wafer-level optical elements and the concave spacer-wafer apertures in which they are formed are disclosed. The wafer-level optical elements include a spacer wafer comprising a plurality of apertures. Each aperture has a concave shape in a planar cross-section of the spacer wafer and an overflow region intersecting the planar cross-section. The wafer-level optical elements also include an array of optical elements, each optical element of the array being formed of cured flowable material within a respective one of the plurality of apertures. A portion of the cured flowable material forming each optical element extends into the overflow region of the respective aperture of the plurality of apertures. The spacer wafer includes a plurality of apertures, each of the plurality of apertures having a concave shape in a planar cross-section of the spacer wafer. Each of the plurality of apertures includes an overflow region intersecting the planar cross-section.

Concave spacer-wafer apertures and wafer-level optical elements formed therein

A wafer-level method for fabricating a plurality of cameras includes modifying an image sensor wafer to reduce risk of the image sensor wafer warping, and bonding the image sensor wafer to a lens wafer to form a composite wafer that includes the plurality of cameras. A wafer-level method for fabricating a plurality of cameras includes bonding an image sensor wafer to a lens wafer, using a pressure sensitive adhesive, to form a composite wafer that includes the plurality of cameras.

Wafer-level bonding method for camera fabrication

A method for black coating camera cubes at wafer level includes expanding the gap between individual diced camera cubes of the wafer by stretching tape securing the diced camera cubes. The method includes applying a black coating layer to the stretched camera cubes, laser trimming undesired portions of the black coating layer, and removing the undesired portions of the black coating layer.

System and method for black coating of camera cubes at wafer level

The disclosed methodology for buck-boost inverted voltage conversion uses a boost stage coupled to a charge pump stage at a switch node controlled by a transistor switch coupled between the switch node and ground. The boost stage includes a boost inductor coupled between an input supply voltage and the switch node, and the charge pump stage includes a charge pump capacitor coupled between the switch node and a pump node which is coupled to the load and an output capacitor in parallel with the load. The regulated inverted output voltage is supplied to the output capacitor and the load by: (a) in a first phase, switching the transistor switch to conducting to couple the switch node to ground, and thereby (i) transferring energy from a source of input voltage source to the boost inductor, and (ii) transferring energy from a charge pump capacitor to the output node, and (b) in the second phase, switching the transistor switch to non-conducting and clamping the charge pump capacitor at a positive reference voltage, and thereby transferring energy from the boost inductor to the charge pump capacitor. In one embodiment, the positive reference voltage is the input voltage (i.e., during the second phase, the charge pump capacitor is clamped to the input voltage).

Inverting buck-boost using single-inductor boost and charge pump with a grounded switch

An apparatus for suppressing power bus bouncing in a hot-swappable system has been developed. The apparatus includes a connection module with three interior pins for: the power return; the power supply; and the system ground. The system ground pin is shorter than the other two so that it makes contact with the power bus after the bouncing from the return and supply pins has subsided.

Growing community of inventors

San Jose, CA, United States of America

Alan Dean Martin