Texas Instruments Corporation

Alan Davis

Timothy David Anderson

Duc Quang Bui

Reid E Tatge

Kai Chirca

Todd T Hahn

Dheera Balasubramanian Samudrala

Jonathan F Humphreys

Naveen Bhoria

Jerald G Leach

Todd M Snider

Alexander Tessarolo

Laurence Ray Simar, Jr

Raj Kanagasabai

Joseph R Zbiciak

Natarajan Kurian Seshan

Venkatesh Natarajan

Soujanya Narnur

Rama Venkatasubramanian

Sahithi Krishna

Laurence R Simar

Gary L Swoboda

Ching-Yu Hung

Eric J Stotzer

David Peter Foley

Mel Alan Phipps

Leland J Szewerenko

Ajay Jayaraj

Richard H Scales

Paul Arthur Gingrich

Paul Fuqua

Jiuling Liu

Jonathan Dzoba

Edmund Sim

Timothy John Harvey

Kenneth E Aron

Sambandam Manohar

Jadadeesh Sankaran

James Nagurne

A method for writing data to memory that provides for generation of a predicate to disable a portion of the elements so that only the enabled elements are written to memory. Such a method may be employed to write multi-dimensional data to memory and/or may be used with a streaming address generator.

System and method for predication handling

Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

Conditional branch instructions

A method for compiling and executing a nested loop includes initializing a nested loop controller with an outer loop count value and an inner loop count value. The nested loop controller includes a predicate FIFO. The method also includes coalescing the nested loop and, during execution of the coalesced nested loop, causing the nested loop controller to populate the predicate FIFO and executing a get predicate instruction having an offset value, where the get predicate returns a value from the predicate FIFO specified by the offset value. The method further includes predicating an outer loop instruction on the returned value from the predicate FIFO.

Nested loop control

In an example, a system includes a processor, where the processor includes a plurality of processor registers, and where the processor is configured to execute a first instruction in a first execution context. The processor is also configured to receive a PRESERVE instruction that indicates at least one processor register among the plurality of processor registers. The processor is configured to, responsive to the PRESERVE instruction, preserve parameters in the at least one processor register and clear other processor registers in the plurality of processor registers in the first execution context. The processor is also configured to execute a second instruction in a second execution context.

Securing registers across security zones

A method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof, wherein each non-consecutive data elements of a register is retrieved to be stored to interleave with each non-consecutive data elements of a different register upon an executive of an interleaving store instruction, wherein a mask instruction directing a lane of a storage space in which the non-consecutive data elements are stored is executed in conjunction with the interleaving store instruction, and wherein a processor of a second type is configured to emulate a processor of a first type to store the non-consecutive data elements the same as non-consecutive data elements stored in the first type processor.

Method of storing register data elements to interleave with data elements of a different register, a processor thereof, and a system thereof

A nested loop controller includes a first register having a first value initialized to an initial first value, a second register having a second value initialized to an initial second value, and a third register configured as a predicate FIFO, initialized to have a third value. The second value is advanced in response to a tick instruction during execution of a loop. In response to the second value reaching a second threshold, the second register is reset to the initial second value. The nested loop controller further includes a comparator coupled to the second register and to the predicate FIFO and configured to provide an outer loop indicator value as input to the predicate FIFO when the second value is equal to the second threshold, and provide an inner loop indicator value as input to the predicate FIFO when the second value is not equal to the second threshold.

A digital data processor includes an instruction memory storing instructions specifying data processing operations and a data operand field, an instruction decoder coupled to the instruction memory for recalling instructions from the instruction memory and determining the operation and the data operand, and an operational unit coupled to a data register file and an instruction decoder to perform an operation upon an operand corresponding to an instruction decoded by the instruction decoder and storing results of the operation. The operational unit is configured to perform a table recall in response to a look up table read instruction by recalling data elements from a specified location and adjacent location to the specified location, in a specified number of at least one table and storing the recalled data elements in successive slots in a destination register. Recalled data elements include at least one interpolated data element in the adjacent location.

Look-up table read

A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Reducing overhead in processor array searching

A digital data processor includes an instruction memory storing instructions each specifying a data processing operation and at least one data operand field, an instruction decoder coupled to the instruction memory for sequentially recalling instructions from the instruction memory and determining the data processing operation and the at least one data operand, and at least one operational unit coupled to a data register file and to an instruction decoder to perform a data processing operation upon at least one operand corresponding to an instruction decoded by the instruction decoder and storing results of the data processing operation. The operational unit is configured to increment histogram values in response to a histogram instruction by incrementing a bin entry at a specified location in a specified number of at least one histogram.

Histogram operation

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San Diego, CA, United States of America

Alan Davis