Texas Instruments Corporation

Alan David Hales

Lee Doyle Whetsel

Neil John Simpson

Timothy David Anderson

Mujibur Rahman

Lewis Nardini

Ramakrishnan Venkatasubramanian

Rubin Ajit Parekhji

William Cronin Wallace

Anthony Martin Hill

Sumant Dinkar Kale

Srivaths Ravi

Rajesh Kumar Tiwari

Srujan Kumar Nakidi

A built-in self-test (BIST) method includes providing expanded test patterns to a logic circuit under test, generating a first signature based on a response of the logic circuit to the expanded test patterns, generating a second signature based on the first signature, wherein the second signature is a compressed version of the first signature, selecting one of the first signature or the second signature in response to a control signal, comparing the selected one of the first signature or the second signature to an expected signature, and, based on the comparison of the selected one of the first signature or the second signature to the expected signature, determining that the logic circuit passes or fails BIST.

Re-programmable self-test

The PRPG provides the test stimulus to the circuit, but it can only generate a finite number of care-bits from any given input seed which limits the maximum coverage that can be achieved. The only way to increase the coverage is to provide additional seed input data to the PRPG. The on-chip one time only programmable eFuse is used to store new PRPG seed data inputs and corresponding MISR output signature data for comparison. An XOR circuit option on the output of the MISR is operable to further compress the output data.

Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Functional core circuitry with serial scan test expected, mask circuitry

IC expected data and mask data on I/O data pads

Apparatus and method for testing an integrated circuit. An integrated circuit includes circuitry to be tested, scan chain logic, and a test adapter. The scan chain logic is configured to transfer test data to and test results from the circuitry. The test adapter is configured to extract the test data from a packet received from an automated test control system and to transfer the test data to the scan chain logic. The test adapter is also configured to receive the test results from the scan chain logic, and to packetize the test result for transmission to the automated test control system.

Packet based integrated circuit testing

Integrated circuit wafer having plural dies with each die including test circuit receiving expected data and mask data from different pads

Integrated circuit wafer having integrated circuit die with plural comparators receiving expected data and mask data from different pads

Integrated circuit with plural comparators receiving expected data and mask data from different pads

IC with comparator receiving expected and mask data from pads

Integrated circuit die having input and output circuit pads, test circuitry, and multiplex circuitry

IC dies with serarate connections to expected and mask data

A multibit combined multiplexer and flip-flop circuit has a plurality of bit circuits. Each bit circuit includes and input section, a flip-flop section and a per bit control section. The input sections have inputs for plural of input signals and corresponding input pass gates. The outputs of the input pass gates are connected to the input of the flip-flop section. Each per bit control section includes an inverter for each input terminal. There is a combined control section receiving a clock signal and a control signals for selection of only one of the input signals. The combined control section include a logical AND for each input signal combining the clock signal and the selection signal. The output of each logical AND is connected to the input of a corresponding inverter of each per bit control circuit. The input pass gate are controlled by a corresponding logical AND and said corresponding inverter.

Family of multiplexer/flip-flops with enhanced testability

An embodiment of the invention provides system for detecting faults on a test chain. A circuit provides a test signal to an input of a test chain. The test chain includes a plurality of buffers connected in series. A register receives a logical value representing the output of the test chain. The register sends the logical value representing the output of the test chain to test circuitry where the value is observed.

Test chain testability in a system for testing tri-state functionality

In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.

Delay fault testing using distributed clock dividers

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Richardson, TX, United States of America

Alan David Hales