Standard Microsystems Corporation

Agere Systems Inc.

Lucent Technologies Inc.

Smsc Holdings Sarl

Other

Agere Systems Guardian Corp.

Alan David Berenbaum

Raphael Weiss

Richard Wahler

Tor E Jeremiassen

Nevin C Heintze

Stefanos Kaxiras

Eileen Marando

Drew Jon Dutton

Hubert Rae McLellan, Jr

Alexander Gibson Fraser

Robert B Dianda

Uri Segal

Jury Muchin

Nevin Heintze

A system to control access to a nonvolatile memory. The system includes an embedded controller, and a nonvolatile memory including a password. The embedded controller and the nonvolatile memory may be in communication with one another. The system further includes a lock register receiving and storing the password from the nonvolatile memory, and a key register receiving a key from the embedded controller and holding the key for one machine cycle. Further, the system includes a comparator connected between the lock register and the key register. The comparator compares the password received from the lock register and the key received from the key register. Output from the comparator is provided to an access filter connected between the embedded controller and the nonvolatile memory. Based on the comparator output, the access filter may grant or block access to the nonvolatile memory.

Method and system for controlling access to embedded nonvolatile memories

The present disclosure provides an improved point-to-point serial peripheral interface, a system comprising an improved point-to-point serial peripheral interface, and a method for use in a system comprising an improved point-to-point serial peripheral interface. A master comprises a SPI initiating port. Each slave comprises at least one SPI receiving port and at least one SPI forwarding port. The master provides a set of SPI signals to the SPI receiving port of the first slave in the chain, and the entire SPI signals are forwarded via the SPI forwarding port of each of the slaves until the SPI transaction reaches a target slave, which is identified by an in-band device addressing mechanism.

Point-to-point serial peripheral interface for data communication between devices configured in a daisy-chain

The present disclosure provides a system and method for implementing extensible hardware configuration using memory. A memory containing an Info Block is provided. The Info Block contains a set of descriptors, which comprises an address part and a data part. The OTP Engine reads each valid descriptor stored in the Info Block, and writes the data in the data part into the memory location specified by the address part. The OTP Engine interacts with the Info Block by accessing the Info Block Controller registers via the central system bus.

Extensible hardware device configuration using memory

A system including a serialized secondary bus architecture. The system may include an LPC bus, an I/O controller, a serialized secondary bus, and at least one slave device. The LPC bus may be connected to the I/O controller, and the at least one slave device may be connected to the I/O controller via the serialized secondary bus. The serialized secondary bus has a reduced pin count relative to the LPC bus. The I/O controller may receive bus transactions from the LPC bus. The I/O controller may translate and forward LPC bus transactions to the at least one device over the secondary bus. The I/O controller may include a processing unit. The processing unit may initiate bus transactions intended for the at least one slave device. The I/O controller may also include a bus arbitration unit. The bus arbitration unit may arbitrate ownership of the secondary bus between the processing unit and the LPC bus.

Serialized secondary bus architecture

Techniques for using structured virtual registers in embedded systems are described. A virtual register structure definition provides a map of virtual registers within an embedded controller. The virtual registers are externally accessible and correspond to memory locations within the embedded controller. In various embodiments, an embedded controller and/or an external entity may store data in or read data from the virtual registers using the virtual register structure definition. The problems of manual tracking of virtual register addresses and manual transcription of virtual register addresses to program code are ameliorated. When the virtual register map changes, logical references in program code to particular virtual registers need not necessarily be changed.

Structured virtual registers for embedded controller devices

System and method for authenticating data or program code via a configurable signature. Configuration information is retrieved from a protected first memory, e.g., an on-chip register, where the configuration information specifies a plurality of non-contiguous memory locations that store the signature, e.g., in an on-chip memory trailer. The signature is retrieved from the plurality of non-contiguous memory locations based on the configuration information, where the signature is useable to verify security for a system. The signature corresponds to specified data and/or program code stored in a second memory, e.g., in off-chip ROM. The specified data and/or program code may be copied from the second memory to a third memory, and a signature for the specified data and/or program code calculated based on the configuration information. The calculated signature may be compared with the retrieved signature to verify the specified data and/or program code.

Configurable signature for authenticating data or program code

System and method for implementing one time programmable (OTP) memory using embedded flash memory. A system-on-chip (SoC) includes a cleared flash memory array that includes an OTP block, including an OTP write inhibit field that is initially deasserted, a flash memory controller, and a controller. Data are written to the OTP block, including setting the OTP write inhibit field to signify prohibition of subsequent writes to the OTP block. The SoC is power cycled, and, in response, at least a portion of the OTP block is latched in a volatile memory, including asserting an OTP write inhibit bit based on the OTP write inhibit field, after which the OTP block is not writeable. In response to each subsequent power cycling, the controller is held in reset, the latching is performed, the controller is released from reset, and the flash array, now write protected, is configured to be controlled by the controller.

Implementation of one time programmable memory with embedded flash memory in a system-on-chip

Temperature readings obtained within a computer system from the location of monitored circuit elements may be oversampled at least three times, and a median average of the three parameter readings rather than the arithmetic mean may be used for controlling a device, e.g. a fan, configured to regulate the environmental parameter, e.g. temperature, a the location of the monitored circuit elements. For example, when a CPU temperature reading is requested by the system comprising the CPU, a thermal monitoring system may acquire at least three consecutive temperature readings of the CPU, discard the highest temperature reading and the lowest temperature reading, and return the median reading to be used in controlling a fan configured to regulate temperature at the location of the CPU, resulting in more accurate temperature readings and more accurate fan control. In various implementations, more than three readings may be considered at a time, and running averages based on median values may be computed in a variety of ways to obtain a temperature control value to control the fan.

Processor temperature measurement through median sampling

An embedded controller capable of providing direct memory access (DMA) to memory for a host. The controller may include a processor, a memory medium, and an interface coupled to the memory medium. The interface may be configured to couple to a host and receive a DMA request. The DMA request may include a request to read data from a memory location in the memory medium or a request to write data to a memory location in the memory medium. The DMA request may include a relative memory address. The interface may be configured to translate the relative memory address into a first address of the memory medium. Accordingly, the interface may perform operations according to the DMA request using the first address of the memory medium. The processor may be configured to operate according to data stored in the memory medium.

External direct memory access of embedded controller memory

In-band event polling mechanism. A master device may initiate a polling transaction to poll at least a subset of a plurality of slave devices for event information. In response to the polling transaction, at least one of the subset of slave devices may transmit event information to the master device. The event information may correspond to at least one of a plurality of asynchronous event types. If the event type associated with the received event information is an event notification for an embedded processor of the master device, the master device may forward the event information to the embedded processor. Otherwise, if the event type associated with the received event information is an event notification for a device external to the master device (e.g., a host processor), the master device may translate the event information to a protocol associated with the event type and forward the event information to the external device.

In-band event polling

System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

Enhancing security of a system via access by an embedded controller to a secure storage device

System and method for protecting data in a system including a main processor, an embedded controller, and a memory. In response to a power-on-reset (POR), access to the memory is enabled, e.g., access by the embedded controller. First data is read from the memory (e.g., by the embedded controller) in response to the enabling, where the first data are usable to perform security operations for the system prior to boot-up of the main processor. The first data are used, e.g., by the embedded controller, to perform one or more security operations for the system, then access to the memory, e.g., by the embedded controller, is disabled, where after the disabling the memory is not accessible, e.g., until the next POR initiates enablement.

Memory protection for embedded controllers

Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device may transmit data to one or more of the slave devices at a rate of one bit per clock cycle. One or more of the slave devices may transmit data to the master device at a rate of one bit per two consecutive clock cycles. The master device may sample the transmitted data on the second cycle of each two consecutive clock cycle period. Alternatively, the slave devices may transmit data to the master device at a rate of one bit per N consecutive clock cycles, where N&#x2267;2, and the master device may sample the transmitted data on the Ncycle of each N consecutive clock cycle period.

Two-cycle return path clocking

A power state broadcast mechanism. A master device may broadcast a message through the use of a protocol to each of one or more slave devices to inform the slave devices of the power state of a computer system. The broadcast message may include a protocol header indicating the start of the broadcast transaction, a function type parameter indicating the type of broadcast transaction, and power state data indicating the power state of the computer system. Each of the slave devices may read the protocol header to detect the start of a broadcast transaction, and the function type parameter to determine the type of broadcast transaction. If the function type parameter indicates a power state broadcast transaction, each of the slave devices may read the power state data included in the broadcast message and determine whether to adjust the current power state of the slave device.

Method, system, and apparatus for a plurality of slave devices determining whether to adjust their power state based on broadcasted power state data

An address assignment mechanism. A computer system may include one or more types of slave devices. Each slave device includes an internal device ID. Slave devices of the same type include the same internal device ID. The master device may broadcast a message through the use of a protocol to each of the slave devices to initiate an address assignment operation. Each of the slave devices determines whether the broadcast device ID included in the broadcast message matches the internal device ID associated with the slave device. If the broadcast device ID matches the internal device ID, the linear bus address included in the broadcast message is assigned to the slave device. The bit size of the linear bus address may be smaller than that of the broadcast device ID. After the address assignment operation, the master device may communicate with the slave device using the assigned linear bus address rather than the device ID.

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New York, NY, United States of America

Alan David Berenbaum