Infineon Technologies Ag

Qimonda Ag

Qimonda North America Corporation

Alan Daniel

Christopher Kunce

Benjamin Louis Heilmann

In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a plurality of memory bank segments physically separated from each other and from the first set of memory banks. Each memory bank segment is arranged adjacent to, and occupies less area than, one of the memory banks of the first set.

Multi-bank memory device method and apparatus

An integrated circuit includes one or more memory array segments configured to store information and a refresh controller. Each memory array segment has a plurality of memory cells arranged in rows selectable through a row address. The refresh controller is configured to monitor row address activity to identify which bits of the row address change state at least once during a memory access operation and to skip refresh of the rows associated with the row address bits that do not change state at least once during the memory access operation.

Memory refresh method and apparatus

An oscillator according to the present invention reduces power consumption by enlarging the pulsewidth of an oscillator output pulse. Since this pulse disables an oscillator current source, the enlarged pulsewidth reduces the time the current source is enabled. When a first capacitor charges to at least a reference voltage, a differential amplifier produces a low level signal that is provided to a latch generating the output pulse. The low level signal controls the latch to produce and maintain a high level signal until the latch is triggered. The latch signal disables the current source, while enabling a transistor to transfer charge from the first capacitor to a second capacitor. When the second capacitor attains a sufficient voltage, the latch is triggered to produce a low level signal, thereby enlarging the pulsewidth of the output pulse. The low level signal enables the current source and facilitates discharge of the second capacitor.

Apparatus and method for reducing power consumption within an oscillator

A system of multiplexed data lines in a DRAM integrated circuit includes a switching circuit having two switching states. In one switching state, the data lines connect to a first configuration of data paths as would occur in a typical DRAM integrated circuit. A limited number of spare column select lines are available to repair defective column select lines in the first configuration. In another switching state, the data lines connect to a second configuration of the data paths, doubling the number of spare column select lines available to repair a defective column select line.

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Durham, NC, United States of America

Alan Daniel