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Hewlett-packard Company

Convex Computer Corporation

Alan D Gant

David M Chastain

Thomas M Jones

Arthur T Kimmel

David A Nobles

Gary Belgrave Gostin

Steven Jeffrey Wallach

David M Patrick

Harold Wallace Dozier

John W Clark

James R Weatherford

James E Mankovich

Jeffrey H Gruger

Michael C Harris

Steven M Rowan

Kent A Fuka

Frank J Marshall

Gilbert J Hansen

John M Golenbieski

Gaynel J Lockhart

Harold D Shelton

Gerald Matulka

Michael E Sydow

Larry W Spry

Robert B Kolstad

William H Wallace

The multi-node multiprocessor system with globally shared memory is partitioned into groups of nodes called error containment clusters of nodes or ECCNs. The nodes would be partitioned such that an ECCN resides on a column of nodes or a row of nodes. Within each ECCN there is coherent memory sharing. Between the ECCNs, the communication is through a messaging protocol. The memory within each node is also partitioned into protected and unprotected memory. Unprotected memory is used for messaging and protected memory is used for sharing. A failure in an error containment cluster would corrupt the memory within that cluster, specifically the protected memory within that cluster and also the unprotected memory used by that cluster to communicate with the other clusters. However, the other clusters could continue to run because their protected memory would be unaffected, and could continue to communicate through the remaining unprotected memory.

Error containment cluster of nodes

A communication bus (14) provides bidirectional data communication between a computer (12) and various peripheral units including input/output processors (18, 20) and a service processor (22). The computer includes a memory control unit (24) which is connected to a memory array (26). A central processor unit (30) is connected for data exchange with the memory control unit (24). Data blocks are transferred through the bus (14) and either originate or terminate at the memory array (26). A peripheral unit, such as the processor (18) transfers a data block by first transferring a header parcel (146) which defines an address, block length and type of function. This is transmitted to the memory control unit (24) which carries out the desired data transfer by sending or receiving sequential data parcels. An interrupt bus (16) connects each of the units of the computer system (10) including the processors (18, 20, 22) and the central processing unit (30). Any one of the units connected to the interrupt bus ( 16) can interrupt any of the other units. The interrupt process comprises sending an interrupt vector through interrupt lines (66). At the receiving unit the interrupt is identified and the appropriate function carried out. The combination of the communication bus and the interrupt bus (16) comprises an input/output bus for the computer system (10) to provide a high data bandwidth together with flexible operation.

Input/output bus for system which generates a new header parcel when an

A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first microinstruction. In a still further aspect of the computer there is included the logical data cache which stores data at logical addresses such that the central processor can store and retrieve data without the necessity of first making a translation from logical to physical address.

Computer system

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Garland, TX, United States of America

Alan D Gant