Atmel Corporation

Alan Chen

Stanley Hong

Jami Wang

Neville B Ichhaporia

Stephen Trinh

Vijay P Adusumilli

Graham H M Stout

Ivan N Kutzarov

A dynamic column redundancy replacement system for programming and reading a non-volatile memory system includes an input data replacement logic block and an output data replacement logic block. A column redundancy match logic block compares a user address to latched fuse addresses of bad columns and identifies address matches to facilitate the replacement of bits from defective memory cells with replacement redundancy bits.

Dynamic column redundancy replacement

The present invention provides a solution for long master bit lines in a large capacity memory device. A master bit line is partitioned by at least one switching transistor placed on the master bit line.

Memory architecture with advanced main-bitline partitioning circuitry for enhanced erase/program/verify operations

A column redundancy system for a non-volatile memory includes a separate companion controller chip that includes a column redundancy RAM memory array for storing addresses of defective non-volatile memory cells. Column redundancy match logic provides a match output signal corresponding to a match of a particular user input address for the non-volatile memory with the address of a defective non-volatile memory cell, the collection of said addresses stored in the column redundancy RAM memory array. Column redundancy replacement logic, in response to a match output, dynamically substitutes correct data associated with a defective non-volatile memory cell into an I/O program or read data bit stream of the non-volatile memory chip.

Column redundancy RAM for dynamic bit replacement in FLASH memory

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Saratoga, CA, United States of America

Alan Chen